Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1993-12-03
1999-03-23
Chaudhuri, Olik
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
438 14, 438613, H01L 2358
Patent
active
058863621
ABSTRACT:
An integrated circuit die is tested by inserting test probe needles into flat solder pads before reflow. The testing is performed at different temperatures to functionally test the integrated circuit die. The solder pads are flat during probe test to improve the uniform contact point and pressure for the test probes, and help avoid slippage or sliding. The probe needles may cause indentation in the solder pads. Following probe test, the solder pads are reflowed to transform the solder pads into solder bumps. Reflow after probe test removes any indentations from the solder pads created during the probe test and leaves only rounded solder bumps without probe damage. The solder bumps are used to flip-chip interconnect the IC into end user systems.
REFERENCES:
patent: 4273859 (1981-06-01), Mones et al.
patent: 4814283 (1989-03-01), Temple et al.
patent: 5002895 (1991-03-01), LaParquier et al.
patent: 5289631 (1994-03-01), Koopman et al.
Millican Lavoie R.
Winchell, II Vern H.
Atkins Robert D.
Chaudhuri Olik
Kelley N
Motorola Inc.
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