Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of...
Reexamination Certificate
2002-12-17
2004-09-07
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Radiation or energy treatment modifying properties of...
C438S514000, C438S706000, C438S725000
Reexamination Certificate
active
06787484
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor wafer photolithographic patterning processes and more particularly to a method for reducing visible light induced charge accumulation and consequential subsequent time dependent dielectric arcing (TDDA) (arcing) phenomena causing damage in microelectronic integrated circuitry.
BACKGROUND OF THE INVENTION
As critical dimensions have become smaller and integrated circuit (IC) integration density increases, charge buildup and arcing has become increasingly problematical in microelectronic IC fabrication processes. For example, as the thickness of dielectric insulating layers is reduced between conductive charge carrying portions of a multi-layer semiconductor device, the electric field strength, which is inversely proportional to the dielectric thickness spanning an electric field caused by electrical charge accumulation, increases dramatically. In many cases, in a multi-layer semiconductor device formed in multiple dies over a semiconductor wafer process surface, electrical charges may become temporarily trapped in one area and migrate over time to other areas, preferentially accumulating at certain portions of the multi-layer device. For example, surfaces including defects, for example vacancies and interstitials at the surface of a dielectric portion of the multi-layer device may preferentially accumulate electrical charges of one sign, inducing the accumulation of charges of the opposite sign on an opposite surface of a thickness of the dielectric portion creating an electric field. The presence of conductive circuitry, for example formed of copper or alloys thereof, extends throughout the multiple layers of the device allows electrical charge to migrate and preferentially accumulate over time following an electrical charge producing process.
Over time, sufficient charge buildup may occur over a sufficiently thin dielectric portion to create substantial electric field strength which exceeds the dielectric breakdown strength of the dielectric resulting in dielectric breakdown. As a result, certain portions of the integrated circuitry in the device become defective leading to rejection of the device.
One process that leads to electrical charge accumulation in semiconductor devices are plasma enhanced processes such as deposition and etching which produce localized non-uniform charge densities over the semiconductor wafer surface during the plasma enhanced process. The imbalance in electrical charges in both the semiconductor wafer and the plasma may induce electrical discharge arcing damaging the semiconductor wafer process surface. For example, charge accumulated over time and trapped within the semiconductor device may provide a source of charge imbalance and subsequent arcing during the plasma process.
The problem of dielectric breakdown has been enhanced by the increasing use of low-k (dielectric constant) materials. For example, many of the low-k materials, including carbon doped silicon oxide are porous, have lower mechanical strength, and may be prone to a higher degree of charge buildup through charge trapping processes. Consequently, the factors of thinner dielectric layer portions, higher electrical charge densities and lower dielectric breakdown strength combine to enhance the incidence and susceptibility to dielectric breakdown. In addition, electric discharges such as arcing more easily produces damage within such dielectrics, creating areas of localized micro-cracking.
Arcing damage frequently occurs in the dielectric insulator/metal conductor interfaces, where conductive interconnect lines provide an electrical pathway to preferentially move electrical charges to produce localized charge imbalance regions in the various dielectric insulating layers. The problem is critical since the damage caused by arcing is frequently severe enough to make further processing of the wafer impractical or seriously impact reliability. As a result, arcing damage to the wafer is costly in terms of wafer yield and reliability.
There are a number of semiconductor manufacturing processes that are associated with producing charge imbalances within portions of a semiconductor process wafer during the course of manufacturing multiple layers of device circuitry. The prior art has not sufficiently addressed methods to reduce or avoid time dependent dielectric arcing (TDDA) as the problem has not become sufficiently acute until recently as critical dimensions approach 0.1 micron and below. TDDA has been associated with the apparent spontaneous occurrence of dielectric arcing events over time in the presence of no discernable triggering events.
There is therefore a need in the semiconductor processing art to develop semiconductor manufacturing processes including a method whereby electrical charge imbalance accumulation in semiconductor devices is reduced such that arcing including time dependent dielectric arcing (TDDA) is reduced or avoided thereby improving device yield and reliability.
It is therefore an object of the invention to provide a method whereby electrical charge imbalance accumulation in semiconductor devices is reduced such that arcing including time dependent dielectric arcing (TDDA) is reduced or avoided thereby improving device yield and reliability while overcoming other shortcomings and deficiencies of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for reducing electrical discharges within semiconductor wafers.
In a first embodiment, the method includes providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process wafer; and, limiting the semiconductor process water to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
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patent: 4595837 (1986-06-01), Wu et al.
patent: 5858879 (1999-01-01), Chao et al.
patent: 6479820 (2002-11-01), Singh et al.
patent: 6605484 (2003-08-01), Janos et al.
Lu Yun-Cheng
Yao Chih-Hsiang
Nguyen Ha Tran
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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