Method of reducing variable retention characteristics in...

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S149000

Reexamination Certificate

active

06898138

ABSTRACT:
The illustrated embodiments relate to reducing variable retention time in dynamic random access memory (DRAM) integrated circuit devices. Memory cells that comprise the DRAM device are placed in a reverse bias condition. While under reverse bias, the DRAM device is maintained at an elevated temperature for a predetermined time.

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