Method of reducing the number of configuration bits by...

Details Method of reducing the number of configuration bits by... Method of reducing the number of configuration bits by...

2006-01-10

2006-01-10

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000, C716S030000

Reexamination Certificate

active

06985011

ABSTRACT:
Apparatus and method configures a programmable logic device (PLD). The method includes reading a first configuration frame from the PLD. The first configuration frame indicates used and unused bit positions. The method further includes reading a second configuration frame from a memory. The second configuration frame is related to the first configuration frame. The method further includes creating a third configuration frame by placing information from the second configuration frame into positions indicated by the first configuration frame. The method further includes configuring the PLD using the third configuration frame. In this manner, the second configuration frame may occupy less space in the memory, and may be read more quickly, than a frame that also included position information.

REFERENCES:
patent: 5773993 (1998-06-01), Trimberger
patent: 6150839 (2000-11-01), New et al.
patent: 6201406 (2001-03-01), Iwanczuk et al.

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