Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-28
2003-11-04
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06642579
ABSTRACT:
FIELD OF THE INVENTION
This invention is generally related to silicon-on-insulator (SOI) CMOS devices, and more particularly, to a method for reducing the body resistance in a body contacted MOSFET (BC-MOSFET) device to avoid a floating body effect.
BACKGROUND OF THE INVENTION
SOI CMOS has become the mainstream technology for high performance microprocessor applications. This technology continues migrating towards thinner SOI thicknesses to further reduce the parasitic capacitance and improve the short channel effect. A significant obstacle to thinner SOI films is that the body resistance increases drastically. A low body resistance is essential for SOI CMOS technology because many circuit applications require the use of a body contacted MOSFET (BC-MOSFET) to avoid the floating body effect. This invention is intended to solve the problem of body resistance in SOI films thinner than 100 nm without complicating the process.
Many patents exist that are related to solving the problem of the extrinsic body resistance in SOI, all of which use a complex process to form the body contact. As a result, the added processing makes the patents inappropriate for conventional SOI CMOS technologies. By way of example, U.S. Pat. No. 5,962,895 describes an SOI transistor having a self-aligned body contact that uses a complex method of inserting a body contact next to the source. The SOI transistor has a self-aligned body contact formed through an extension to the gate, which makes it possible to form the body contact with a minimal increase in area and avoids the need to connect the source to the body, as conventional schemes require, and more particularly, of having the body contact pass through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture. A conformal layer is then deposited that is subsequently etched to create aperture-defining sidewalls. The contact aperture is etched next to define sidewall members that support the insulating sidewalls and segregate the collecting electrode from the gate, source and drain. Since the raised source drain process is highly complex, this method cannot be used for a conventional SOI technology.
U.S. Pat. No. 6,156,589 describes a compact SOI body contact link, the result of a complex method of inserting a body contact using epitaxial growth of the substrate at the device edge. The body contact is formed epitaxialy from the substrate to the body region of the device. The body contact is self-aligned with the gate and is buried within the isolation region outside the active area of the device. Thus, the body contact does not increase the parasitic capacitance within the device, nor does the body contact affect the device density. No additional metal wiring or contact holes are required. Again, epitaxial growth is too complex to be used for SOI.
U.S. Pat. No. 5,767,549 describes an SOI CMOS structure incorporating a substrate, a layer of insulation, a layer of silicon having raised mesas and thin regions therebetween to provide ohmic conduction between the mesas, between the electronic devices on the mesas and interconnecting wires. This invention overcomes the problem of the floating gate due to an accumulation of charge below the channel of the MOSFET. Thus, a modified MESA isolation allows for two devices to share the same body contact. However, the MESA does not reach the BOX and, as such, it shares the bottom silicon for the body contact link. This method requires a modified MESA isolation and epitaxial growth process which is again too complex for conventional SOI devices.
U.S. Pat. No. 6,177,708 describes another SOI FET body contact structure wherein a self-aligned SOI FET device with an “L” shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices having the same gate geometry are placed side-by-side in a single silicon island opening that accommodates but a single device and a “T” shaped gate structure. The devices, in accordance with this invention, are formed using standard SOI processing steps. An aspect of this invention includes the use of novel SOI devices with their body and source connected to each other for a variety of circuit applications, e.g., memory cell sense amplifiers and the like, where high speed operation necessitates the use of SOI technology, but where physical space considerations limit their application. This patent is limited to an L-shaped body contact, and being one of the first ones to make use of an L-shaped body contact MOSFET, it is characterized by a high extrinsic body resistance in an ultra-thin film SOI environment.
U.S. Pat. No. 5,405,795 describes a method of forming an SOI transistor having a self-aligned body contact. The body contact is formed through an extension to the gate such that the body contact introduces a minimal increase in area and avoids connecting the source to the body, as characteristic of conventional constructions that require passing the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using the sidewalls to define sidewall members that support the insulating sidewalls to isolate the collecting electrode from both the gate and source/drain. This patent is limited to T-shape structures and requires a highly complex raised source/drain process too complicated for use in a conventional SOI technology
U.S. Pat. No. 5,965,917 describes a method of forming body contacts in SOI MOSFETs to eliminate floating body effects. The SOI MOSFET includes a silicon layer and an insulator layer positioned over a silicon substrate. The isolation region defines a silicon region positioned over the insulation layer. The silicon region further includes a source region, a drain region, and a doped body region. A first metal conductor is electrically coupled to the side and top of the source region and the side of the body region. The first metal conductor establishes a potential at the body region to control the floating body effect. A second metal conductor is electrically coupled to the top of the drain region. Herein, the source/drain do not reach the buried oxide (BOX). The metal straps the edge at the source side to short the source to the body. This structure precludes that the source and drain extend to the bottom of the SOI film. However, in today's commercial SOI technologies, the source and drain diffusion always extend to the BOX to minimize the parasitic junction capacitance.
U.S. Pat. No. 5,652,454 describes a semiconductor device on an SOI substrate. A field oxide film is formed to cover a surface of the SOI layer and reach the surface of the buried oxide film. As a result, a PMOS active region of the SOI and an NMOS active region of the SOI can be totally electrically isolated, preventing a latch-up. As a result, it is possible to provide a device on an SOI substrate which can implement a high level of integration by eliminating the reduction of the breakdown voltage between the source and drain, known to be a problem for conventional SOI field effect transistors (FETs). It further disposes the body contact region very efficiently, which hampers high integration and its method of manufacturing. NFETs and PFETs are completely isolated but by a deep STI/LOCOS. The source and drain do not touch the BOX. Thus, the body contact can easily be constructed. Again this structure requires that the source/drain not extend to the bottom of SOI film which increases significantly the parasitic junction capacitance.
U.S. Pat. No. 5,185,280 describes a method of fabricating an SOI MOSFET with pocket implant and body-to-source (BTS) contact. The transistor has an implanted region having the same conductivity type as the body underneath. The back gate threshold voltage is enhanced to reduce the possibility of back gate current flowing. In addition to the pocket implants and body contact, a
Schnurmann H. Daniel
Zarabian Amir
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