Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-11-01
2005-11-01
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S424000, C438S435000, C438S437000, C438S696000, C438S734000, C438S743000
Reexamination Certificate
active
06960530
ABSTRACT:
A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.
REFERENCES:
patent: 5610441 (1997-03-01), Carl et al.
patent: 6255194 (2001-07-01), Hong
patent: 6828239 (2004-12-01), En-Ho et al.
patent: 2005/0020027 (2005-01-01), Lim et al.
Chen Yi-Nan
Liao Hung-Chang
Wu Chang-Rong
Wu Kuo-Chien
Goudreau George A.
Nanya Technology Corporation
Quintero Law Office
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