Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2001-01-11
2003-02-18
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S098000
Reexamination Certificate
active
06522171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits and, in particular, to power requirements of integrated circuit chips.
2. Description of Related Art
Integrated circuit chips have power requirements which become increasingly critical as the trend continues toward making circuits smaller and more dense, and operating such devices from battery power. There is constant motivation to reduce chip power usage due to packaging requirements, as well as applications in portable devices which have limited battery power.
A typical prior art low voltage dynamic circuit is shown in FIG.
1
. This dynamic logic circuit performs the INVERT logical operation (i.e., INPUT=A, OUTPUT={overscore (A)}) In operation of the circuit, a negative active pulse, PC is initially provided at the gate of transistor P
1
to precharge the output node, OUT, to VDD. The voltage at node OUT is held high by the latch formed by inverters I
1
and I
3
. When input signal A rises to a low voltage logic level 1, the node OUT falls to the ground or logic level ‘0’. Note that transistor N
1
is a low threshold transistor. In some semiconductor technologies, transistor devices with different threshold voltage values are offered. As an example, a technology may offer a standard threshold transistor and a low threshold transistor with 0.6 volts and 0.2 volts, respectively. Recalling that transistor N
1
is a low threshold transistor, there is an increase in the overdrive associated with the low voltage signal A received at its gate terminal. After a predefined time, the node OUT is precharged to VDD by a negative active pulse, PC, which is provided at the gate of transistor P
1
. When the circuit or the chip that it operates upon enters standby mode, input signal A will be a logic level 0 and the node OUT will be latched at a logic level 1. This enables a sub-threshold leakage path from V
DD
(logic level ‘1’) to ground (logic level ‘0’) through the low threshold transistor N
1
. The sub-threshold leakage is proportional to the width of the device. If this type of circuit is frequently used on an integrated circuit chip with wiring at the sub-micron level, the sub-threshold leakage could be in the range of microamperes, which is considered excessive.
One known solution in the prior art is shown in FIG.
2
. The circuit adds a standard threshold transistor N
2
between the drain of transistor N
1
and the drain of transistor P
1
that limits the sub-threshold leakage. This circuit requires an additional device N
2
, which has a higher threshold voltage than transistor N
2
, and therefore has the disadvantage of resulting in increased size and degraded performance if the circuit is used to drive a bus. Another known prior art solution is shown in FIG.
3
. This circuit limits the sub-threshold leakage by decreasing the logic level ‘0’ from ground down to negative voltages, e.g., −1V to −2V. This solution is undesirable since it has increased power dissipation associated with the larger voltage swing (from V
NEG
to V
DD
) at node A. Accordingly, there exists a long-felt need for a method to reduce the amount of sub-threshold leakage associated with circuits utilizing low threshold devices and thereby reduce standby or sleep mode current leakage.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and system which reduces the amount of sub-threshold leakage associated with circuits utilizing low threshold devices.
It is another object of the present invention to provide a method and system which increases integrated circuit chip performance by reducing standby or sleep mode current leakage.
A further object of the invention is to provide an improved integrated circuit chip for use in low power and portable devices.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a dynamic logic circuit having reduced sub-threshold leakage current during standby mode which comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.
The device coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage may comprise a PFET transistor coupled between the upper power rail and the output node which, upon receipt of a standby signal, maintains the potential of the output node at the potential of the upper power rail. Alternatively, the device comprises an NFET transistor coupled between the lower power rail and the output node which, upon receipt of a standby signal, maintains the potential of the output node at the potential of the lower power rail.
The dynamic logic circuit may include a transistor coupled to the at least one upper power rail and the output node adapted to set the potential of the output node to the upper power rail voltage upon receipt of the precharge signal, and at least one transistor coupled to the lower power rail and the output node adapted to set the potential of the output node to the lower power rail potential upon receipt of the evaluation signal. The device coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage is then adapted to set the output node to the lower power rail potential upon receipt of the standby signal.
In one embodiment the dynamic logic circuit includes a first transistor coupled to the at least one upper power rail and the output node adapted to set the potential of the output node to the upper power rail voltage upon receipt of the precharge signal, a second transistor coupled to the lower power rail, third and fourth transistors serially coupled between the second transistor and the first transistor and output node, and a fifth transistor coupled between the second transistor and the first transistor and output node. The second, third, fourth and fifth transistors are adapted to set the potential of the output node to the lower power rail potential upon receipt of the evaluation signal. The device coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage comprises a transistor coupled to the lower power rail and the output node adapted to set the output node to the lower power rail potential upon receipt of the standby signal.
In another embodiment, the dynamic logic circuit includes a first transistor coupled to the at least one upper power rail and the output node adapted to set the potential of the output node to the upper power rail voltage upon receipt of the precharge signal, and a pair of second and third transistors serially coupled to the lower power rail and the output node adapted to set the potential of the output node to the lower power rail potential upon receipt of the evaluation signal. The device coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage comprises a transistor coupled to the lower power rail and the output node adapted to set the output node to t
Hanson David R.
Kirihata Toshiaki
Mueller Gerhard
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