Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-27
2002-04-16
Chaudhuri, Olik (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S666000, C438S669000, C438S697000, C438S758000, C438S926000
Reexamination Certificate
active
06372626
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit devices and fabrication methods therefor, and more particularly to integrated circuits including conductive lines thereon and fabrication methods therefor.
BACKGROUND OF THE INVENTION
Integrated circuits are widely used in consumer and commercial applications. As is well known to those having skill in the art, integrated circuits generally include a large number of active devices in an integrated circuit substrate, and one or more layers of conductive lines, also referred to as wiring layers, on the integrated circuit substrate, to form interconnections for the active devices in the substrate.
As the integration density of integrated circuits continues to increase, it may become increasingly difficult to form high density conductive lines on integrated circuit substrates. More specifically, as the integration density of integrated circuit devices continues to increase, one or more steps may be created on the integrated circuit substrate due to varying topography thereof. Due to these steps, it may become increasingly difficult to perform a high density photolithographic process to define conductive lines, because the depth-of-focus margin may increase.
The depth-of-focus problem is illustrated in
FIG. 1
, which is a cross-sectional view of an integrated circuit. In
FIG. 1
, at least one layer
131
is formed on an integrated circuit substrate
141
, such as a silicon semiconductor substrate. The layer
131
has a step of height h. A conductive layer is blanket formed on the layer
131
. A photoresist
111
is formed on the conductive layer, to thereby pattern first and second conductive lines
121
and
122
, and a conductive connector line
123
therebetween.
Unfortunately, however, the first conductive line
121
is elevated on the integrated circuit substrate relative to the second conductive line
122
, due to the nonuniform topography of the underlying layer
131
. Since the conductive layer that comprises conductive lines
121
,
122
and
123
has a step, it may be difficult to obtain proper depth-of-focus for patterning the conductive layer using the photoresist layer
111
. It therefore may be difficult to perform accurate patterning. Accordingly, one or more of the conductive lines
121
,
122
and
123
may break. As the thickness and/or width of the conductive lines
121
,
122
and
123
continues to decrease, and the step height h of the insulating layer
131
continues to increase, reliability and/or other problems caused by the increased depth-of-focus margin may be exacerbated.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming conductive lines on integrated circuit substrates, and integrated circuits so formed.
It is another object of the present invention to provide methods that can reduce step heights between first and second conductive lines that are laterally spaced apart on an integrated circuit substrate, and integrated circuits so formed.
These and other objects can be provided according to the present invention, by methods of reducing a step height between first and second conductive lines that are laterally spaced apart on an integrated circuit substrate, wherein the first conductive line is elevated on the integrated circuit substrate relative to the second conductive line, to create a step. According to the invention, a dummy conductive line is formed beneath the second conductive line, to further elevate the second conductive line on the integrated circuit substrate, and thereby reduce the step height between the first and second conductive lines. The second conductive line and the dummy conductive line vertically overlap by an amount that is less than one half the width of the second conductive line. Depth-of-focus thereby may be improved, so that reliability of the conductive lines also may be improved. Moreover, the capacitance between the second conductive line and the dummy conductive line may be reduced. It will be understood that as used herein, “vertically” indicates a direction that is generally orthogonal to the laterally extending faces of the integrated circuit substrate, and does not indicate an absolute orientation.
More particularly, according to the present invention, a dummy conductive line is formed on an integrated circuit substrate. First and second conductive lines are then formed on the integrated circuit substrate, such that the second conductive line vertically overlaps the dummy conductive line by an amount that is less than one half the width of the second conductive line, to thereby reduce a step height between the first and second conductive lines compared to absence of the dummy conductive line while allowing reduced capacitance between the second conductive line and the dummy conductive line. The first and second conductive lines preferably are formed by forming a conductive layer on the integrated circuit substrate including on the dummy conductive line, and patterning the conductive layer to define the first and second conductive lines, such that the second conductive line vertically overlaps the dummy conductive line by an amount that is less than one half the width of the second conductive line. An insulating layer may be formed on the dummy conductive line prior to forming the first and second conductive lines.
The dummy conductive line and the first and second conductive lines may comprise metal, polysilicon and/or other known conductors. The dummy conductive line may be connected to a power supply voltage, a ground voltage, a signal voltage, or may remain floating. However, the dummy conductive line is formed beneath the second conductive line, so as to reduce the step height between the first and second conductive lines while allowing reduced capacitance, rather than to perform a signal carrying function in the integrated circuit.
Integrated circuits according to the present invention comprise an integrated circuit substrate, a dummy conductive line on the integrated circuit substrate and first and second conductive lines on the integrated circuit substrate, such that the second conductive line vertically overlaps the dummy conductive line by an amount that is less than one half the width of the second conductive line, to thereby reduce a step height between the first and second conductive lines compared to absence of the dummy conductive line. Accordingly, the step height may be reduced, to thereby allow improved depth of focus, and thereby allow improved reliability of integrated circuit devices to be obtained. Moreover, capacitance between the second conductive line and the dummy conductive line may be reduced.
REFERENCES:
patent: 5281555 (1994-01-01), Cho
patent: 5534728 (1996-07-01), Kim et al.
patent: 63104451 (1988-05-01), None
Chae Bong-seok
Kyung Kye-hyun
Myers Bigel & Sibley & Sajovec
Rao Shrinivas H.
LandOfFree
Method of reducing step heights in integrated circuits by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of reducing step heights in integrated circuits by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing step heights in integrated circuits by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2836694