Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-07-22
2003-12-16
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S227000, C365S233100, C327S156000, C327S158000
Reexamination Certificate
active
06665219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory integrated circuit, and more specifically to a method and apparatus for reducing power consumption by a memory integrated circuit.
2. Description of the Related Art
In a double data rate (DDR) random access memory (RAM), it is desirable to have output data retrieved from memory and placed on an output bus synchronously with an external clock. Conventionally, this is achieved by including a data buffer, referred to as a DQ buffer, among the functional circuitry of the integrated circuit. The DQ buffer includes a set of latches having respective data inputs attached to an internal data bus, a set of respective data outputs attached to an external data bus, and one or more clock inputs. In response to a signal transition at the clock input of a data latch, the latch loads data available at the data input of the latch and makes it available at the latch data output, in effect transferring data from the internal data bus to the external data bus.
Also conventional is the use of a signal delay device, such as a delay locked loop (DLL) circuit timed by a free running external clock. The delay locked loop produces a plurality of delayed clock signals corresponding to, but lagging in phase, the free running external clock. Each data latch receives a delayed DLL clock signal produced by the delay locked loop to clock the clock input of the latch.
The delay locked loop includes a delay line. The delayed DLL clock signals of the delay locked loop are produced by passing the external clock signal through this delay line. The delay line consists primarily of a group of delay elements connected in series such that the output of a first delay element is operatively connected to the input of a second delay element and the output of the second delay element and is operatively connected to the input of a third delay element and so on. Typically a delay element includes at least one logic gate. Each of the of delay elements has a characteristic delay such that a signal introduced at its input produces a signal at its output after a period of time equal to the characteristic delay. Accordingly, by placing a number of delay elements in series and feeding a digital signal sequentially through the series of delay elements a delay of finite duration may be introduced into the propagation of the signal. When a signal transition is applied at the input of the DLL, each of the series of delay elements undergoes a state transition after a delay related to the number of preceding delay elements in the series. It is thus apparent that the delay is cumulative with the number of elements that must transition, and the result is a signal delay proportional to the number of delay elements in the delay line. In a delay locked loop circuit, this number of delay elements can be varied to insure that the delay produced corresponds to the period of the external clock, less a small time allowed for signal transmission of a clock signal from the DLL to a latch of the DQ buffer.
It is a general characteristic of transistors, and hence of electronic gates and delay elements constructed with transistors, that state transitions cause a dissipation of energy. Accordingly, in making the state transitions described above, the delay elements of a DLL dissipate a certain amount of power.
Because, there is a relatively large number of delay elements in a delay line, and because each of these elements must transition, or toggle, with each transition of the external clock, the DLL circuit represents a locus of some power dissipation in a DRAM integrated circuit, particularly in a double data rate (DDR) DRAM. Generally, this power loss is tolerable, and is necessary for functioning of the chip. Nonetheless, saving all, or a portion, of the energy dissipated in toggling of the delay elements of the DLL would be advantageous.
SUMMARY OF THE INVENTION
The present invention reduces the power consumption of an integrated circuit by eliminating unnecessary cycling of a delay locked loop circuit during a power down mode of operation of a DRAM. Power down mode is a mode of operation during which system power is conserved. In a preferred embodiment, when the integrated circuit is placed in a power down mode, the integrated circuit of the invention interrupts transmission of a free running external clock signal that is otherwise received by an input of the delay locked loop. Because the delay locked loop does not receive the external clock signal, the delay elements of the delay line of the delay locked loop do not toggle. Rather, the delay elements of the delay line remain in a constant state as long as the integrated circuit continues to receive power and the delay locked loop does not receive the clock signal. Since operation of electronic logic gates in a constant state requires less power than operation of the same gates in transition, a power savings is realized.
In one aspect of the invention, the integrated circuit is manufactured with a switch. The switch is most commonly a circuit, made of gates, implemented with transistors. The switch circuit is electrically connected in series with a conductive line that connects the external clock to the external clock input of the delay locked loop. The switch circuit can be switched to be non-conductive during power down. When the switch is nonconductive, transmission of the external clock signal is interrupted by the switch circuit, and the delay locked loop does not receive the external clock signal.
Accordingly, the invention includes a method of reducing the power consumption of a random access memory integrated circuit by preventing a delay locked loop, or other internal clock producing circuit, from receiving an external clock signal during a power down mode. In another aspect, the invention includes an embodiment of a memory integrated circuit including a switch, e.g. a transistor based gate circuit, electrically connected in series with a conductive trace adapted to operatively connect an external clock with an external clock input of a delay locked loop or other internal clock producing circuit.
In various other aspects, the invention includes methods and embodiments adapted to otherwise prevent toggling of the delay line of a delay locked loop when the DLL clock signal produced by that loop is not required, as during operation in power down mode.
REFERENCES:
patent: 5815462 (1998-09-01), Konishi et al.
patent: 5926053 (1999-07-01), McDermott et al.
patent: 5990730 (1999-11-01), Shinozaki
patent: 6084802 (2000-07-01), Shinozaki
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6194938 (2001-02-01), Waldrop
patent: 6310822 (2001-10-01), Shen
patent: 6437619 (2002-08-01), Okuda et al.
patent: 6438060 (2002-08-01), Li et al.
Li Wen
Loughmiller Daniel R.
Schaefer Scott
Thomann Mark R.
Auduong Gene N.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
LandOfFree
Method of reducing standby current during power down mode does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of reducing standby current during power down mode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing standby current during power down mode will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3165929