Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-06-07
2011-06-07
Kebede, Brook (Department: 2894)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257SE21562
Reexamination Certificate
active
07956417
ABSTRACT:
Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
REFERENCES:
patent: 6815278 (2004-11-01), Ieong et al.
patent: 6825534 (2004-11-01), Chen et al.
patent: 6830962 (2004-12-01), Guarini et al.
patent: 6864534 (2005-03-01), Ipposhi et al.
patent: 6870226 (2005-03-01), Maeda et al.
patent: 7060585 (2006-06-01), Cohen et al.
patent: 2004/0152276 (2004-08-01), Nishimura
patent: 2004/0195646 (2004-10-01), Yeo et al.
patent: 2004/0256700 (2004-12-01), Doris et al.
patent: 2004/0266128 (2004-12-01), Chen et al.
patent: 2005/0104156 (2005-05-01), Wasshuber
patent: 2005/0116290 (2005-06-01), de Souza et al.
patent: 2006/0024931 (2006-02-01), Chan et al.
patent: 2006/0105536 (2006-05-01), Cheng et al.
patent: 2006/0154429 (2006-07-01), de Souza et al.
patent: 2006/0284251 (2006-12-01), Hsu et al.
patent: 2106034 (1990-04-01), None
patent: 11017001 (1999-04-01), None
B. Doris, et al. “Simplified Hybrid Orientation Transistor (SHOT) for High Performance CMOS”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 86-87.
M. Yang, et al., “On the Integration of CMOS with Hybrid Crystal Orientations”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 160-161.
M. Yang, et al., “High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations”, 2003 IEDM pp. 03-0453 through 03-0456.
Black Linda
Domenicucci Anthony G.
Fried David M.
Holt Judson R.
Sheraw Christopher D.
International Business Machines - Corporation
Kebede Brook
MacKinnon Ian D.
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