Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2008-01-15
2008-01-15
Sarkar, Asok K. (Department: 2891)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S401000, C438S687000, C257SE21232
Reexamination Certificate
active
07319073
ABSTRACT:
A wafer has thereon a plurality of integrated circuit die areas, scribe line that surrounds each of the integrated circuit die areas, and a laser marking region having therein a laser marking feature. A pad layer is formed on the wafer. AA photoresist pattern is formed on the pad layer. The AA photoresist pattern includes trench openings that expose STI trench areas within the integrated circuit die areas and dummy openings that merely expose a transitioning region of the laser-marking region. The pad layer and the substrate are etched through the trench openings and dummy openings, to form STI trenches within the integrated circuit die areas and dummy trenches in the transitioning region. A trench fill dielectric is deposited over the wafer and fills the STI trenches and the dummy trenches. Using the pad nitride layer as a polish stop layer, chemical mechanical polishing the trench fill dielectric.
REFERENCES:
patent: 6181018 (2001-01-01), Saino
patent: 6194287 (2001-02-01), Jang
patent: 6368937 (2002-04-01), Nakamura
patent: 2004/0033689 (2004-02-01), Ho et al.
patent: 2004/0185637 (2004-09-01), Fu et al.
patent: 2005/0158966 (2005-07-01), Fang et al.
Anya Igwe U.
Hsu Winston
Sarkar Asok K.
United Microelectronics Corp.
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