Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-02-01
2001-04-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S595000, C438S300000, C438S301000, C438S303000, C438S305000, C438S655000, C438S660000, C438S663000, C438S664000, C438S657000
Reexamination Certificate
active
06211048
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application ser. no. 87121315, filed Dec. 21, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. Particularly, the present invention relates to a method of manufacturing a salicide layer and more particularly, to a method of manufacturing a salicide layer on a gate structure.
2. Description of the Related Art
Usually, silicide is formed On the gates, the source/drain region or the interconnects to lower the contact resistance between the semiconductor devices on a substrate. Since lattice of the silicide is rearranged when it is treated by high-temperature annealing, the defects in the silicide are eliminated, wherein the defects are eliminated, and perfect grains are grown instead of defective grains. A crystalline structure is formed in the silicide after a high-temperature annealing is performed so that the resistance of the silicide is lowered. Hence, the contact resistance can be reduced by forming a silicide layer on the gates, the source/drain region or the interconnects. Currently, the process of self-aligned silicide (salicide) is widely used in the integrated circuits industry.
FIGS. 1A through 1B
are schematic, cross-sectional views of the conventional process for manufacturing a salicide layer on a semiconductor substrate.
As shown in
FIG. 1A
, a substrate
100
having agate structure
102
is provided. A light implantation step is used to form a lightly doped source/drain region
110
adjacent to the gate structure
102
in the substrate
100
. A spacer
104
is formed on the sidewall of the gate structure
102
. The gate structure
102
comprises a gate oxide layer
106
and a gate electrode
108
.
As shown in
FIG. 1B
, a heavy implantation step is used to form a source/drain region
112
in the substrate
100
exposed by the gate structure
102
and the spacer
104
. A titanium layer (not shown) is formed over the substrate
100
. A thermal process is performed to convert portions of the titanium layer above the gate electrode
108
and the source/drain region
112
into a silicide layer
114
, which is a titanium nitride layer. The remaining titanium layer, which is not converted into the silicide layer, is stripped away to finish the process of manufacturing a salicide layer.
Since portions of silicon in or on the gate electrode
108
and the source/drain region
112
diffuse to the spacer
104
to spread onto the surface of the spacer
104
as temperature is rises, a silicide layer
116
is formed on the spacer
104
, when the silicide layer
114
is formed on the gate electrode
108
and the source/drain region
112
. In such a circumstance, when the silicide layer
116
connects the gate electrode
108
and the source/drain region
112
, it results in a bridging effect. Hence, an undesired electrical coupling occurs between semiconductor devices, and the yield is low.
In order to prevent bridging effects from occurring between the devices, the thermal process is performed at a relatively low temperature of about 700-750° C. to reduce the diffusion of the silicon from the gate electrode
108
and the source/drain region
112
into the spacer
104
, especially from the surface portion of the gate electrode, which results in the lateral formation of salicide. However, the relatively low temperature of the thermal process produces a salicide with a relatively poor quality, so the goal of reducing the contact resistance cannot be achieved.
Therefore, there is a need to provide a method for reducing salicide lateral growth, which maintains the desired performance between semiconductor devices and avoids the bridging effect therebetween.
SUMMARY OF THE INVENTION
The invention provides a method of reducing salicide lateral growth. In accordance with the present invention, the bridging effect caused by the lateral salicide formation will be minimized and the quality of the salicide layer will be improved as well.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of reducing salicide lateral growth. A substrate having a gate structure and an anti-reflection layer on the gate structure is provided. A spacer is formed on the sidewall of the gate structure and the anti-reflection layer. The anti-reflection layer is removed to expose the gate structure, wherein the gate structure and the spacers together form a recess structure. A salicide layer is formed on the gate structure in the recess structure and on the substrate. Since the recess structure is formed by a combination of the gate electrode and the spacers, the diffusion of the silicon from the top surface portion of the gate electrode to the surface of the spacer can be avoided while the thermal process is performed at a relatively high temperature. Therefore, the bridging effect caused by the lateral salicide formation cannot occur. Additionally, the weakness of the poor quality of the salicide formed by the thermal process with a relatively low temperature to prevent the devices from the bridging effect can be removed. Furthermore, because of the thick salicide layer formed on the gate electrode in the recess structure, the quality of the salicide is enhanced and the contact resistance is extremely reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Hung Tsung-Yuan
Hwang Tsing-Fong
Hack Jonathan
Huang Jiawei
J C Patents
Niebling John F.
United Microelectronics Corp.
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