Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-28
2003-01-07
Chaudhan, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S634000, C438S687000, C438S637000, C438S672000
Reexamination Certificate
active
06503827
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the semiconductor industry, and more particularly, to the formation of a semiconductor device having reduced planarization defects.
2. Related Art
Planarization processes, such as chemical mechanical polishing (CMP), are often utilized at various stages of semiconductor manufacturing. Unfortunately, these commonly used planarization processes often produce yield detractors or defects, such as scratches, trenches formed by dishing or erosion that create puddles of conductive material, and so on. Often these defects reproduce in subsequent layers of a semiconductor device, resulting in potential shorts, reduced production yields, etc.
Accordingly, there exists a need in the industry for a method of reducing the defects produced during planarization processes.
SUMMARY OF THE INVENTION
A first general aspect of the present invention provides a method of forming a semiconductor device, comprising: (a) providing a substrate; (b) depositing a sacrificial layer over a surface of the substrate; (c) forming an at least one interconnection feature within the substrate and the sacrificial layer; (d) depositing a liner within the interconnection feature; (e) depositing a conductive material over the surface of the substrate; (f) planarizing the substrate; and (g) removing the sacrificial layer.
A second general aspect of the present invention provides a method of forming a semiconductor device, comprising: providing a substrate having a first sacrificial layer formed on the substrate; forming at least one first interconnection feature within the substrate and the first sacrificial layer; depositing a first liner within the at least one first interconnection feature; depositing a first conductive material over a surface of the substrate; planarizing the substrate; and removing the first sacrificial layer.
A third general aspect of the present invention provides a method of reducing the formation of defects during semiconductor manufacture, comprising: (a) providing a substrate; (b) depositing a sacrificial layer on the substrate; (c) forming at least one interconnection feature within the sacrificial layer; (d) depositing a conductive material over a surface of the substrate; (e) planarizing the surface of the substrate; and (f) removing the sacrificial layer having defects produced therein from the planarizing.
The foregoing and other features of the invention will be apparent from the following more particular description of the embodiments of the invention.
REFERENCES:
patent: 4541168 (1985-09-01), Galie et al.
patent: 4758306 (1988-07-01), Cronin et al.
patent: 4936950 (1990-06-01), Doan et al.
patent: 4997746 (1991-03-01), Greco et al.
patent: 5008216 (1991-04-01), Huang et al.
patent: 5286675 (1994-02-01), Chen et al.
patent: 5625232 (1997-04-01), Numata et al.
patent: 5783490 (1998-07-01), Tseng
patent: 5798299 (1998-08-01), Chung
patent: 5801093 (1998-09-01), Lin
patent: 5817574 (1998-10-01), Gardner
patent: 5910020 (1999-06-01), Yamada
patent: 5932907 (1999-08-01), Grill et al.
patent: 6037216 (2000-03-01), Liu et al.
patent: 6090699 (2000-07-01), Aoyama et al.
patent: 6103455 (2000-08-01), Huang et al.
patent: 6103569 (2000-08-01), Teo et al.
patent: 6150272 (2000-11-01), Liu et al.
patent: 6159845 (2000-12-01), Yew et al.
patent: 6159846 (2000-12-01), Yew et al.
patent: 6165895 (2000-12-01), Lin
patent: 6168989 (2001-01-01), Chiang et al.
Planarization Process Using Spin-On-Glass and Polishing, Research Disclosure, Jun. 1991, No. 326, Kenneth Mason Publications Ltd, England, 1 page.
Producing Integral Via and Pad Metallurgy, A. P. David and A. M. Flannery, IBM Technical Disclosure Bulletin, vol. 14, No. 1, Jun. 1971, p. 101.
Bombardier Susan G.
Feeney Paul M.
Geffken Robert M.
Horak David V.
Rutten Matthew J.
Chaudhan Chandra
International Business Machines - Corporation
Nguyen Thanh
Schmeiser Olsen & Watts
Walter, Jr. Howard J.
LandOfFree
Method of reducing planarization defects does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of reducing planarization defects, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing planarization defects will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3063453