Method of reducing pin holes in a nitride passivation layer

Details Method of reducing pin holes in a nitride passivation layer Method of reducing pin holes in a nitride passivation layer

1997-12-03

2000-08-15

Nelms, David

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438775, 438787, 438659, 438688, 438788, 438792, 438798, H01L 2131

Patent

active

061036390

ABSTRACT:
A metal interconnection is formed on a dielectric layer. A pre-treatment is then performed to remove organic materials on the surface of the metal layer. The pre-treatment is done by plasma bombardment using NH.sub.3 and NO.sub.2 as the reaction gases. A thin oxide layer is subsequently deposited on the metal layer and on the dielectric layer. The oxide layer serves a buffer layer to eliminate the stress between the metal layer and subsequent silicon nitride layer. A silicon nitride layer is then formed on the thin oxide layer to act as a passivation layer.

REFERENCES:
patent: 5262279 (1993-11-01), Tsang et al.
patent: 5753319 (1998-05-01), Knapp et al.
patent: 5807787 (1996-12-01), Fu et al.

Affiliated with

Also associated with

Rating

Method of reducing pin holes in a nitride passivation layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of reducing pin holes in a nitride passivation layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing pin holes in a nitride passivation layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2006549