Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-12-28
2002-06-04
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06399487
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of integrated circuit manufacture with particular reference to reducing the temperature of annealing during a SALICIDE process.
BACKGROUND OF THE INVENTION
In the course of manufacturing an integrated circuit, the problem often arises of having to make contact to very small areas that are located very close together. In particular, two silicon regions may be separated by a very narrow band of silicon oxide. A common example of this is the source and drain of a field effect transistor which are separated from the gate pedestal contact by very small insulating spacers. To deal with this the SALICIDE (self aligned silicide) process was developed. This takes advantage of the fact that a metal such as titanium (also cobalt and tungsten have been used) when heated for a short time (of the order of seconds) to a temperature of about 800° C. very rapidly reacts with any silicon with which it is in contact to form titanium silicide. On the other hand, no reaction will occur between titanium and the silicon oxide so that a selective etchant that removes titanium while not attacking titanium silicide, can be used after the RTA to selectively remove all unreacted titanium, leaving material in-place only where titanium had been in contact with silicon.
Although the SALICIDE process, as described above, works very well, there is a secondary problem. It turns out that the structure of the titanium silicide resulting from the RTA described above is a crystalline type known as C-49. This particular structure has a relatively high bulk resistivity (50-60 microhm cm). Fortunately, the crystalline structure of the titanium silicide can be transformed to a different arrangement (known as C-54 and having a bulk resistivity of about 13-20 microhm cm.) by applying an additional heat treatment. In the past, the temperature needed to achieve this crystalline transformation has been about 750-800° C. However, it has been found that as device dimensions continue to shrink the required transformation temperature has risen because an associated decrease in grain size reduces the probability for nucleation and growth of the C-54 phase. Unfortunately, these higher transformation temperatures cause the titanium silicide to agglomerate, so that its sheet resistance rises precipitously.
Thus, there exists a need for a SALICIDE process wherein the transformation temperature to the lower resistivity crystal structure does not exceed about 900° C. An approach commonly taken in the prior art has been to introduce a layer of molybdenum between the titanium and the silicon prior to heating. The effects of this are illustrated in
FIG. 1
which is a plot of sheet resistance as a function of the RTA temperature. Curve
11
is for pure titanium while curve
12
is for the titanium-molybdenum combination. As can be seen, for pure titanium the transformation occurs at about 750° C. while it has been reduced to about 650° C. for the Ti—Mo combination. On the other hand, the sheet resistance of the final layer has increased from about 4.5 ohms per square for the pure titanium to about 8 ohms per square for the Ti—Mo.
The present invention describes a different approach to solving this problem. As will be shown, the temperature for achieving the transition to the lower resistivity phase may be reduced to as low as 650° C. while at the same time achieving a sheet resistance that is less than 3.5 ohms per square. In the course of searching the prior art no reference that teaches the method of the present invention was discovered. However, several references of interest were found:
Black et al. (U.S. Pat. No. 4,756,927 July 1988) describe how suicides of metals such as titanium, molybdenum and tungsten can be formed in selected areas by exposing a surface to a gas including the fluoride compounds of these metals as well as silane and then irradiating selected areas by means of a laser. They note the possibility of forming germanium suicides by substituting germane for silane. Presumably, alloys comprising one of these metals, along with silicon and germanium, could be formed by including both silane and germane in the reacting gases.
Other applications of silicon-germanium alloys appear to be limited to their use as the prime material for forming an integrated circuit. For example Sameshima et al. (U.S. Pat. No. 5,591,653 January 1997) describe a method of manufacturing a silicon-germanium thin film transistor. Similarly, Saraswat et al. (U.S. Pat. No. 5,250,818 October 1993) describe a germanium-silicon-on-insulator thin film transistor while Hsu et al. (U.S. Pat. No. 5,726,459 March 1998) also describe fabrication of a silicon-germanium MOS transistor.
Grider et al. (U.S. Pat. No. 5,646,073 July 1997) show a method of forming a silicon-germanium alloy.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a method whereby selective contact may be made to silicon regions in close proximity to insulating regions.
Another object of the invention has been to provide an improved SALICIDE process wherein a second rapid thermal anneal (for the purpose of reducing the resistivity of the silicide layer) can be accomplished at a lower temperature than is currently achieved in the art.
A still further object of the invention has been that said method result in a sheet resistance for the silicide layer that is at least as low as that obtained when using the conventional SALICIDE process.
These objects have been achieved by coating the structure to which the SALICIDE process is to be applied with a layer of a silicon-germanium alloy prior to the deposition of the titanium layer. Provided there is at least 40 atomic percent of germanium in the alloy a second RTA at a temperature no higher than about 650° C. may be effectively used. The resulting ternary alloy has a resistivity of about 15-20 microhm cm which corresponds to a sheet reistance of about 3-3.5 ohms per square. The ability to achieve low sheet resistance after annealing at such a low temperature becomes increasingly more important as device dimensions decrease since the second RTA becomes increasingly more likely to result in agglomeration of the silicide layer.
REFERENCES:
patent: 4756927 (1988-07-01), Black et al.
patent: 5250818 (1993-10-01), Saraswat et al.
patent: 5591653 (1997-01-01), Sameshima et al.
patent: 5646073 (1997-07-01), Grider et al.
patent: 5726459 (1998-03-01), Hsu et al.
patent: 5915199 (1999-06-01), Hsu
Zhang et al., On the Intrinsic Spacer Layer in Si/SiGe Heterojunction Bipolar Transistor Grown by Ultra High Vacuum Chemical Vapor Deposition. 1997 IEEE/Cornell Conf. on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 8/97. P.109-115.
Chen Lih-Juan
Lai Jane-Bai
Liu Chung-Shi
Yu Chen-Hua
Ackerman Stephen B.
Chaudhuri Olik
Peralta Ginette
Saile George O.
Taiwan Semiconductor Manufacturing Company
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