Method of reducing pattern pitch in integrated circuits

Details Method of reducing pattern pitch in integrated circuits Method of reducing pattern pitch in integrated circuits

2006-09-12

2006-09-12

Ahmed, Shamim (Department: 1765)

Etching a substrate: processes

Masking of a substrate using material resistant to an etchant

C216S047000, C216S074000, C216S079000, C438S689000, C438S947000, C430S311000, C430S313000

Reexamination Certificate

active

07105099

ABSTRACT:
A method of reducing pattern pitch is provided. A material layer, a hard mask layer and a patterned photoresist layer are sequentially formed over a substrate. Using the patterned photoresist layer as etching mask, the hard mask layer is etched. Due to the trenching effect, a residual hard mask layer remains in an exposed region exposed by the photoresist layer and micro-trenches are formed at the edges of the residual hard mask layer. Thereafter, using the residual hard mask layer as etching mask to pattern the material layer. Finally, the patterned photoresist layer and the hard mask layer are removed. In the invention, the trenching effect is utilized when etching the hard mask layer. A portion of the hard mask layer remains, and the micro-trenches are formed in the hard mask layer. After the micro-trenches are transferred to the material layer, the pattern pitch can be reduced.

REFERENCES:
patent: 6475922 (2002-11-01), Zheng
patent: 6878646 (2005-04-01), Tsai et al.
patent: 2003/0222287 (2003-12-01), Tamura

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