Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Utilizing reflow
Patent
1998-05-29
2000-02-15
Chaudhari, Chandra
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Utilizing reflow
438763, 438781, 438783, 438791, H01L 2102
Patent
active
060252790
ABSTRACT:
A method of rapid thermal annealing (RTA) a TEOS oxide layer 50 that underlies a silicon nitride stop layer 60. The RTA of the TEOS-Oxide ILD layer 50 prevents the nitride stop layer 60 and oxide ILD layer 50 from peeling in subsequent thermal steps. The process comprises providing a semiconductor structure 10 with an uneven surface; forming an interlevel dielectric layer 50 composed of PE-TEOS oxide over the structure 10; rapid thermal annealing (RTA) the third interlevel dielectric layer 50 at a temperature between about 850 and 1015.degree. C. for a time between about 10 and 50 seconds; depositing a silicon nitride layer 60 over the third interlevel dielectric layer 50; and planarizing the silicon nitride layer 60 and the third interlevel dielectric layer 50.
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Chiang Min-Hsiung
Huang Jenn Ming
Wang Chen-Jong
Ackerman Stephen B.
Chaudhari Chandra
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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