Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2006-01-10
2006-01-10
Chase, Shelly (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
06986098
ABSTRACT:
The present invention is a method and system for reducing miscorrections of data in a post-processor. In an embodiment of the invention, the system and method may compare a result of an exact match function and a metric for each row of a reconstructed data block to determine if a correction should be made. An algorithm for performing an exact match function may include a column parity check syndrome, a matched filter error syndrome, and an error mask of the present invention. If a result of an exact match function is an exact match, a priority of correction may be given to the row in which the exact match was produced.
REFERENCES:
patent: 6434719 (2002-08-01), Livingston
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patent: 6654924 (2003-11-01), Hassner et al.
patent: 6694477 (2004-02-01), Lee
patent: 6757862 (2004-06-01), Marianetti, II
Christian Kevin G.
Poeppelman Alan D.
Schell David L.
Chase Shelly
LSI Logic Corporation
Suiter West PC
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