Method of reducing leakage current of a semiconductor wafer

Details Method of reducing leakage current of a semiconductor wafer Method of reducing leakage current of a semiconductor wafer

2001-04-10

2002-08-27

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

Reexamination Certificate

active

06440818

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of reducing leakage current of a semiconductor wafer, and more particularly, to a method of etching to reduce leakage current of a semiconductor wafer.
2. Description of the Prior Art
In the field of semiconductor production technology, the measurement of leakage current is a necessary testing tool. The magnitude of the leakage current closely relates to either the lifetime or the current generation rate of the minority carriers. Any defects or damage in the depletion bulk causes an increase of the leakage current.
Please refer to
FIG. 1
to FIG.
3
.
FIG. 1
to
FIG. 3
are schematic diagrams of a self-aligned silicide (salicide) process according to the prior art. In the prior art method, salicide is formed on a semiconductor wafer
10
, the semiconductor wafer
10
comprising a silicon substrate
12
, an active area
16
positioned on the silicon substrate
12
, and a field oxide (FOX) layer
18
positioned on the surface of the silicon substrate
12
. The FOX layer
18
comprises a bird's beak structure
20
that surrounds the active area
16
.
As shown in
FIG. 1
, an ion implantation process is performed to form a P-type doped area
22
in the silicon substrate
12
and within the active area
16
, and then a silicon oxide layer
24
is deposited on the surface of the semiconductor wafer
10
. A photolithographic process is performed to form a photoresist layer
26
, and a salicide block (SAB) mask is used to define a region for the salicide layer.
As shown in
FIG. 2
, a dry etching process is performed after the photolithographic process to remove the silicon oxide layer
24
not covered by the photo resist layer
26
, and then the photo-resist layer
26
is removed completely. In a traditional dry etching process, the range of the top power is about 700 watts. As shown in
FIG. 3
, a salicide process is at last performed to form a salicide layer
28
on the surface of the P-type doped area
22
.
After the salicide process finished, however, a high value of leakage current is measured when a wafer acceptance test (WAT) is performed at the test key of the P-type doped area
22
/N-well
14
. This is due to the high top power of 700 watts of the dry etching process, which destroys the edges of the active region, and sinking of the silicon substrate
12
occurs near the bird's beak structure
20
. The occurrence of so many lattice defects induces the leakage current. Additionally, the same problems happen to the test key of an N-type doped area/P-well. But the salicide layer
28
on the surface of the P-type doped area
22
/N-well
14
is less uniform, so the leakage current value of the P-type doped area
22
/N-well
14
is higher than that of an N-type doped area/P-well.
For dynamic random access memory (DRAM) products, a higher value of the leakage current results in a faster loss of signals in a DRAM cell and a shortened refresh time, and hence a DRAM cell is less steady and electricity is wasted.
SUMMARY OF THE INVENTION
It is therefor an object of the present invention to provide a method of reducing leakage current of the doped area on a semiconductor wafer.
In a preferred embodiment, the present invention provides a method of reducing leakage current of a semiconductor wafer, The semiconductor wafer comprises a silicon substrate, an active area positioned on the silicon substrate, and a field oxide layer positioned on the surface of the silicon substrate surrounding the active area. According to the present invention, a doped area is formed in the silicon substrate and within the active area, and a dielectric layer is deposited on the semiconductor wafer. Then, a dry etching process is performed to remove the dielectric layer. The top power of the dry etching process ranges between three hundred and five hundred watts to prevent damage to the silicon substrate near the field oxide layer and within the active area, and so the leakage current is reduced.
In a second embodiment, the present invention performs a wet etching process to remove the dielectric layer after the dielectric layer is deposited. An anisotropic physical impact to the silicon substrate near the field oxide layer is prevented, and sinking of the salicide layer near the field oxide layer is also prevented. As a result, the leakage current of the doped area is reduced.
In a third embodiment, a dry etching process is performed after the dielectric layer is deposited to etch the dielectric layer to a predetermined height. Then, a wet etching process is performed to remove the dielectric layer. An anisotropic physical impact on the silicon substrate near the field oxide layer is prevented. The dry etching process is performed to shorten the reaction time of the wet etching process.
It is an advantage of the present invention that it prevents an anisotropic physical impact on the silicon substrate near the field oxide layer by a dry etching process with a low power, or by a wet etching process. Sinking in the neighborhood of the field oxide layer is prevented, and hence the leakage of the doped area is reduced.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5554560 (1996-09-01), Hsue et al.
patent: 5736451 (1998-04-01), Gayet
patent: 6255022 (2001-07-01), Young et al.
patent: 6255188 (2001-07-01), Chen et al.

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