Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-11-30
2002-09-03
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S240000, C438S681000, C438S003000, C438S104000
Reexamination Certificate
active
06444580
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION(S)
This application is related to concurrently filed and commonly assigned applications (serial numbers to be assigned) entitled:
“Chemical Solution for Cu—Ca—O thin film formations on Cu Surfaces;”
“Method of Forming Cu—Ca—O Thin Films on Cu Surfaces in a Chemical Solution and Semiconductor Device Thereby Formed;”
“Method of Calcium Doping a Cu Surface Using a Chemical Solution and Semiconductor Device Thereby Formed;”
“Method of Reducing Electromigration in Copper Lines by Calcium-Doping Copper Surfaces in a Chemical Solution and Semiconductor Device Thereby Formed;” and
“Method of Reducing Electromigration in Copper Lines by Forming an Interim Layer of Calcium-Doped Copper Seed Layer in a Chemical Solution and Semiconductor Device Thereby Formed.”
TECHNICAL FIELD
The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the processing of calcium-copper alloy interconnect material and the resultant device utilizing the same. Even more particularly, the present invention relates to reducing and minimizing carbon, sulphur, and oxygen impurities in a calcium-copper alloy interconnect surface.
BACKGROUND OF THE INVENTION
Currently, the semiconductor industry is demanding faster and denser devices (e.g., 0.05-&mgr;m to 0.25-&mgr;m) which implies an ongoing need for low resistance metallization. Such need has sparked research into resistance reduction through the use of barrier metals, stacks, and refractor metals. Despite aluminum's (Al) adequate resistance, other Al properties render it less desirable as a candidate for these higher density devices, especially with respect to its deposition into plug regions having a high aspect ratio cross-sectional area. Thus, research into the use of copper (Cu) as an interconnect material has been revisited, copper being advantageous as a superior electrical conductor, providing better wettability, providing adequate electromigration resistance, and permitting lower depositional temperatures. Cu interconnect material may be deposited by CVD, PECVD, sputtering, electroless plating, and electrolytic plating. However, some disadvantages of using Cu as an interconnect material include etching problems, corrosion, and diffusion into silicon.
1
These problems have sparked further research into the formulation of barrier materials for Cu, which in turn, identified another host of problems associated with the barrier materials themselves (e.g., contamination).
1
Peter Van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, 3
rd
Ed., p. 397 (1997).
In response to interconnect impurity level concerns relating to the fabrication of semiconductor devices having copper (Cu) alloy interconnect surfaces, the industry has been utilizing chemical vapor deposition (CVD) methods. Ca is an inherently highly reactive element in air; therefore, Cu—Ca alloys would behave similarly. Contamination in the Cu—Ca alloys is especially problematic when wet-chemical methods are used for processing. Cu—Ca alloy surfaces have been found to be highly susceptible to carbon (C), sulphur (S), and oxygen (O) contamination, forming an impure layer on the order of 10-20 Å in thickness, as characterized by AES/XPS methods. However, although CVD has been conventionally used for depositing other metal(s) on an interconnect surface, CVD is not a cost-effective method of doping Cu interconnect surfaces with Ca ions. Therefore, a need exists for providing a method of fabricating a semiconductor device having contaminant-reduced Ca—Cu alloy on Cu interconnect surfaces by cost-effectively removing the contaminant layer.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of fabricating a semiconductor device having contaminant-reduced Ca—Cu alloy surfaces formed on Cu interconnects by cost-effectively removing the contaminant layer and a device thereby formed. Contaminant removal from a Cu—Ca—X surface, where contaminant X=C, S, or O, is achieved by sputtering the Cu—Ca—X surface in an Ar atmosphere between the steps of (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Ca—Cu alloy surface onto the underlying Cu interconnect material to form a Ca—Cu/Cu interconnect structure, whereby the sputtering step, under argon (Ar), selectively and effectively removes contaminants from the Cu—Ca—X layer containing higher concentrations of C, S, or O, thereby minimizing the post-annealed contaminant level, and thereby producing a uniform Ca—Cu alloy surface (i.e., Cu-rich with 0.2-5% Ca) on the Cu interconnect material for maximizing Ca—Cu/Cu interconnect structure reliability, electromigration resistance, and corrosion prevention. The annealing step primarily removes O and secondarily removes C and S, especially when performed under vacuum, an inert gas, or a reducing ambient such as ammonia (NH
3
) plasma. Thus, the resultant device then comprises a distinctive contaminant-reduced Ca—Cu/Cu interconnect structure.
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patent: 6291348 (2001-09-01), Lopatin et al.
Peter Van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, (1997), 397, 3rdEdition, McGraw-Hill, USA.
Bernard Joffre F.
King Paul L.
Lopatin Sergey
Advanced Micro Devices , Inc.
Elms Richard
LaRiviere Grubman & Payne, LLP
Menz Dong
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