Method of reducing alignment measurement errors between...

Details Method of reducing alignment measurement errors between... Method of reducing alignment measurement errors between...

2007-03-20

2007-03-20

Thai, Luan (Department: 2891)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

C438S401000, C438S975000, C257S797000, C257SE23179

Reexamination Certificate

active

10864562

ABSTRACT:
An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on the first layer. Portions of the second and/or third layer are selectively removed from regions in and around the first overlay mark. A second overlay mark is formed and aligned to the first overlay mark. The alignment between the second overlay mark and first overlay mark may be measured with an attenuated error due to reflection and refraction or due to an edge profile shift of the first overlay mark.

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