Method of reading and restoring data stored in a...

Details Method of reading and restoring data stored in a... Method of reading and restoring data stored in a...

2002-08-23

2004-09-21

Le, Thong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189040

Reexamination Certificate

active

06795330

ABSTRACT:

TECHNICAL FIELD OF APPLICATION
The present invention relates generally to data storage, and more specifically to a method of reading and restoring data stored in a ferroelectric memory cell.
BACKGROUND
As is well known, electronic memory devices of the non-volatile ferroelectric type integrated in a semiconductor comprise a plurality of non-volatile ferroelectric memory cells that are arranged into rows (wordlines) and columns (bitlines).
Each non-volatile ferroelectric memory cell comprises a MOS selection transistor and a ferroelectric capacitor. The capacitor may be connected to the selection transistor either in series or in parallel. The capacitor oxide is a ferroelectric layer capable of retaining a polarization which can be used to store any information.
If a strong electric field is applied across the capacitor, the polarization in the ferroelectric layer is in the same direction of the applied electric field and remains in that direction until the field is removed. Likewise, if the electric field is applied in the opposite direction, the polarization in the ferroelectric layer is reversed.
Accordingly, as the voltage varies across the capacitor, i.e., as the applied electric field varies, the charge stored on the capacitor follows a hysteretic pattern, as shown in FIG.
1
.
For a ferroelectric material, one defines first and second polarization states, indicated as UP and DOWN in FIG.
1
. Furthermore, a first logic value “0” can be associated with a low polarization state DOWN, and a second logic value “1” associated with a high polarization state UP, this being, of course, but one of two possibilities allowed. Thus, a non-volatile memory cell is obtained.
Two large families of non-volatile FeRAMs are currently in use, which are differentiated by the number of cells that are used for storing a single data bit.
The memory cells of a first family, known as 1T1C, comprise each a selection transistor that is connected in series with a ferroelectric capacitor.
This 1T1C family uses its single cell for storing one information bit. While being advantageous on several counts, the 1T1C family can only provide sensing signals of a limited amplitude.
Referring to
FIG. 2
, to obtain a large sensing signal, a second family of non-volatile memory cells, known as 2T2C, is used which is of the self-referenced architecture. A 2T2C cell
1
basically consists of two 1T1C memory cells. In particular, a first 1T1C cell
1
a
comprises a first selection transistor
2
connected in series with a ferroelectric capacitor
3
.
The series of transistor
2
and capacitor
3
is connected between a first bitline BLT and an auxiliary line PLATE, which is shared by a predetermined number of cells. The control terminal of the selection transistor
2
is connected to a wordline WL.
The terminal that interconnects the transistor
2
and the ferroelectric capacitor
3
will be referred to as the bottom electrode BET hereinafter.
The memory cell
1
also includes a second 1T1C cell
1
b
comprising a second selection transistor
4
connected in series with a ferroelectric capacitor
5
. This series is connected between a second bitline BLC and said auxiliary line PLATE. The control terminal of the selection transistor
4
in the second cell
1
b
is connected to the same wordline WL that is driving the selection transistor
2
in the first cell
1
a.
The terminal that interconnects the transistor
4
and the ferroelectric capacitor
5
will be referred to as the bottom electrode BEC hereinafter.
It should be noted that the capacitors
3
and
5
are polarized in opposite directions at any time except while the cell
1
is being read/written.
By appropriate convention, either a logic 0 or a logic 1 can therefore be stored into the 2T2C cell
1
.
A method of reading a 2T2C cell will now be described with reference to plots vs. time of the signals applied to the cell, and of the polarization conditions of the capacitors
3
and
5
when these signals change, as shown in
FIGS. 3A and 3C
.
For convenience of illustration, it will be assumed that the capacitor
3
connected to the bitline BLT is in a low (DOWN) state, and the capacitor
5
connected to the bitline BLC is in a high (UP) state.
The conventional reading method consists of steps as listed herein below.
Precharging Step
1
In this step, the bitlines BLC, BLT and the auxiliary line PLATE are connected to a low voltage reference (i.e. they are reset).
Read-Pulse Step
2
To apply a read pulse to the memory cell
1
, the auxiliary line PLATE is pulsed to supply voltage VDD, thereby an electric field is applied across the capacitors
3
and
5
.
Referring to
FIG. 3B
, the polarization of capacitor
3
changes, and produces a predetermined voltage V(BLT) on the bitline BLT due to an amount Qsw of charge having in the capacitor. Referring to
FIG. 3C
, the polarization of capacitor
5
does not change, and a voltage V(BLC) is produced on the bitline BLC due to an amount Qln of charge, with the voltage V(BLC) being lower than the voltage V(BLT) presented on bitline BLT.
Reading Step
3
Referring to
FIG. 4
, to actually read the memory cell
1
, a conventional sense amplifier
7
is used which includes two inverters
8
,
9
connected into a latching configuration between a first voltage reference VDD, e.g., the supply voltage, and a second voltage reference GND, e.g., the ground voltage, through respective PMOS and NMOS enable transistors M
1
and M
2
. The inverter
8
comprises a series of PMOS and NMOS transistors
8
a
and
8
b
whose control terminals are connected together and to a common output node OUT of corresponding transistors
9
a
,
9
b
in the other inverter
9
.
During the step of reading the memory cell
1
, the sense amplifier
7
is switched on by application of a low-level signal SAP to the control terminal of the enable MOS transistor M
1
, and by application of a high-level signal SAN to the control terminal of the enable MOS transistor M
2
. This situation causes the voltage level V(BLT) to pull up the bitline BLT and the voltage level V(BLC) to pull down the bitline BLC, thereby enabling the sense amplifier
7
to read out data from the cell
1
.
Restoring Step
4
This step is used to restore the capacitor
3
to its initial state. This is achieved by applying the supply voltage VDD to the bitline BLT and resetting the auxiliary line PLATE.
Referring to
FIGS. 3B and 3C
, it should be noted that the capacitor
5
would already be in its initial state, and both the bitline BLC and the auxiliary line PLATE reset.
Note is also made of that the data stored in the memory cell
1
is presented on the bitlines in digital form, at values that correspond to 0 and VDD, and can be output at any time during Steps
3
or
4
.
Resetting Step
5
This step resets the whole circuit.
Thus, to read data from the 2T2C memory cell
1
, an electric field is generated that pulls up the voltage value on the auxiliary line PLATE. As a result, both cells
1
a
and
1
b
are in the same state, the cell
1
a
that is to change its state (and accordingly referred to as the switch cell) being restored to its initial condition by application of an opposite electric field.
For this purpose, the signal on the auxiliary line PLATE is pulled down, while the voltage on bitline BLT is kept high and equal to the supply voltage reference VDD by the sense amplifier
7
.
Although on several counts advantageous, the reading method just described has some drawbacks. In particular, to apply the real value of the voltage VDD to the common node BET between the transistor
2
and the capacitor
3
from the bitline BLT, the control terminal of the selection transistor
2
, which is connected to the wordline WL, must be bootstrapped with a higher voltage VBOOT, which is equal to the supply voltage VDD plus the threshold voltage Vtn of an N-channel transistor (e.g., the transistor
2
).
The wordline WL is also to be bootstrapped with a relatively high voltage in order to restore the cell
1
to its initial condition, as illustrated by the timing diagram in
FIGS. 3A
to
3

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