Method of reading a four-transistor memory cell array

Details Method of reading a four-transistor memory cell array Method of reading a four-transistor memory cell array

2002-01-31

2003-04-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S207000

Reexamination Certificate

active

06552925

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to CMOS integrated circuits and more particularly to circuits for storing digital data.
SUMMARY OF THE INVENTION
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A a voltage differential between a first supply line and a second supply line causes a current to flow into at least a third supply line depending upon the state of the cell. This current is sensed to read the cell.


REFERENCES:
patent: 5365475 (1994-11-01), Matsumura et al.
patent: 6292388 (2001-09-01), Camarota
patent: 6385081 (2002-05-01), Shiomi

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