Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2000-08-11
2002-06-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S119000, C438S612000, C438S613000, C438S614000, C438S615000, C228S178000, C228S180220, C228S248100, C219S121630
Reexamination Certificate
active
06403399
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to microelectronic packaging, and more specifically to wafer bumping for forming interconnections between a die and a substrate within a package.
Microelectronic packaging may be described as the art and science of establishing interconnections between a die (or a chip) and an application environment in a reliable, functional, and cost effective manner. The die contains the integrated circuit (IC). In most electronic products, there are four major IC devices: the microprocessor, the ASIC (application-specific IC), the cache memory, and the main memory. There are various methods of packaging, including but not limited to PBGA (Plastic Ball Grid Array), CBGA (Ceramic Ball Grid Array), TCP (Tape Carrier Package), and Area-Array Flip Chip Technology.
In Area-Array Flip Chip Technology, the most fundamental level of interconnection is established by wafer bumps, which are typically in the form of solder balls formed on each I/O pad of the die. The wafer bumps have a typical diameter of about 100 microns, and the bump-to-bump distance, or bump pitch, is typically about 225 microns. The process of making bumps on the wafer is called “wafer bumping.”
Current techniques for wafer bumping require design-specific tooling for each new wafer design. The time and cost of manufacturing the tooling is reflected in the new package development cycle, and may result in loss of market share. A recent McKinsey study showed that shipping a product six months late results in a 33 percent loss of the product's lifetime profit.
Several factors are important to consider in choosing a wafer bumping technique. Some techniques are suitable for wafer bumping a large number of wafers of the same design, other techniques are not. Other important factors are the yield statistics and the number of bumps per wafer.
Wafer bumps are generally made of a solder compound. The solder material is placed on the I/O pads of each die on the wafer, and the wafer is passed through one or two re-flow processes to bond the solder to the I/O pads, which gives each bump a spherical shape.
One wafer bumping technique uses a stencil specifically made for each wafer design. The stencil masks the areas outside the I/O pads where the solder compound is unwanted, and a thin layer of solder paste is deposited by, for example, a doctor's blade or a squeegee. The stencil is removed, and the wafer is passed through a re-flow process to melt the paste and to shape the wafer bumps on the I/O pads. Besides requiring a new stencil for each new wafer design, stencils are subject to wear and require regular replacement. Also, the bump yield using stencils is subject to defects in the stencil. Another disadvantage of the stencil technique is that the bump diameter may fluctuate by as much as 20 to 30 microns.
As the requirements for microelectronic devices increase, the number of wafer bumps per die (chip) increases, consequently the wafer bump size must decrease. A current goal is to attach 400,000 wafer bumps onto a wafer having a diameter of 20 cm (8 in). After wafer bumping, the wafer is cut into dice. Preferably, at least 99 percent of the dice should be free of wafer bump defects. A yield this high is statistically very difficult to obtain by currently available techniques.
Once the requirements for an application-specific IC package are determined, an ASIC supplier may develop more than one device design. Before a package is finally qualified, various package builds are evaluated for engineering and prototyping purposes. Specifically, for the pre-mass production stage, there is a need for a rapid and reliable wafer bumping technique so that various device designs and package builds can be evaluated. Preferably, such a technique would also have applications in mass production.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the needs above as well as other needs by providing a method and an apparatus for wafer bumping.
In one embodiment, the invention may be characterized as a method for wafer bumping that includes the steps of spreading a layer of an electrically conductive paste on a surface having a plurality of electrical contacts and exposing a beam-paste interaction volume to the beam of energy to bond a portion of the layer of the electrically conductive paste to at least one of the plurality of electrical contacts for forming a wafer bump.
In another embodiment, the invention may be characterized as an apparatus for wafer bumping that includes an energy source for generating a beam of energy and a positioning device for exposing a beam-paste interaction volume to the beam of energy to bond a portion of a layer of an electrically conductive paste to at least one of a plurality of electrical contacts for forming a wafer bump.
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Chiang Kang-rong
Pekin Senol
Fitch Even Tabin & Flannery
Gurley Lynne A.
LSI Logic Corporation
Niebling John F.
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