Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-31
2004-03-16
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S383000, C257S773000, C257S757000, C257S750000, C257S754000
Reexamination Certificate
active
06707117
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of semiconductors. In particular, the invention relates to electrical interconnects and a method for providing electrical interconnects between regions in a semiconductor device.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor chips, cost is clearly an important concern. Ways are therefore always being looked for to reduce the size of devices in order to allow more devices to fit onto a semiconductor wafer. Also, speed considerations dictate strongly in favor of reduced size. Furthermore, cost is directly impacted by process considerations: especially the number of process steps involved in producing a particular circuit in semiconductor chip form.
Typically, semiconductor devices are built up in layers involving a series of process steps to produce the desired characteristics. For example, a typical semiconductor device such as the device
100
illustrated in
FIG. 1
, may include a polysilicon gate
110
insulated from the underlying silicon substrate by an oxide layer
112
. Two n+ composite regions
114
,
116
are shown and may comprise drain and source regions of a NMOS transistor. The device
100
is separated by shallow trench isolation regions
118
,
120
from adjacent devices
130
,
140
, respectively. As mentioned above, the devices
100
.
130
,
140
are formed in layers. Typically, a silicon substrate is used in which the composite regions
114
,
116
are formed by introducing impurities using one of several possible methods. The shallow trench isolation regions
118
,
120
are formed as isolators between the devices. Thereafter a silicide layer
150
may be formed by depositing a layer of metallic material such as cobalt or titanium and annealing it to react with the silicon to form a silicide. Thereafter the excess, unreacted cobalt or titanium is removed using an etch process. This is followed by depositing a thick oxide layer (TEOS)
152
. In order to provide electrical contacts to specific regions in the device, holes are etched into the TEOS
152
using masking and etching steps, whereafter the holes are filled with metal such as tungsten to define tungsten contacts or plugs
160
,
162
. A metal layer (metal
1
)
170
is then formed on top of the TEOS
152
to contact the contacts
160
,
162
. In order, for example, to interconnect the polysilicon gate
110
and the composite material
180
of adjacent device
140
, contacts
182
,
184
are provided to the polysilicon gate
110
and composite
180
, respectively, as shown in the plan view of FIG.
2
. The metal
1
layer
170
is formed to provide a metal interconnect between the contact
182
and contact
184
.
It will be appreciated that the formation of the interconnect between the polysilicon gate
110
and composite
180
involves quite a number of steps and is space consuming due to the need to build the vertical contacts
182
,
184
and the array of metal traces of the metal
1
layer
170
. The present invention seeks to provide a simpler, more cost effective, and more compact solution for interconnecting regions in a semiconductor device.
SUMMARY OF THE INVENTION
The present invention provides for electrically interconnecting regions in a semiconductor structure, either within a device or between devices by forming metal plugs from the metal used during the formation of the metal silicide layer.
According to the invention, there is provided a method of providing an interconnect between a first region and a second region of a semiconductor device, comprising as part of the process of forming a metal silicide layer, masking off a region that spans across the regions to be interconnected to leave behind, during the etching of the metal used for the silicide layer, a metal interconnect over said regions. Typically the forming of the metal silicide layer includes depositing a metal layer, annealing the metal to form a silicide layer, and etching the unsilicided metal. The method preferably includes providing a mask to selectively etch the unsilicided metal so as to leave behind unsilicided metal over selected areas to be interconnected. The metal may, for example, be cobalt.
Further, according to the invention, there is provided a method of forming an interconnect between two regions in a semiconductor structure, comprising depositing a metal over at least part of the structure, annealing the metal to form a silicide layer, masking off at least one desired portion of the metal, and etching the metal to leave at least part of the silicide layer and the metal over said at least one desired portion, wherein at least one of said at least one desired portions spans across two or more regions of the semiconductor structure. The two or more regions spanned by at least one of the desired portions may be two composite regions or a composite region and a polysilicon region of the same or different devices. For example the regions may be a polysilicon gate of one device, and a n+ or p+ composite region of a different device on the structure. The metal material may be cobalt.
Still further, according to the invention, there is provided a CMOS structure that includes a polysilicon gate, a composite region, and a silicide layer, wherein the polysilicon gate is connected to the composite region by means of a single metal plug contacting the gate polysilicon and composite region, the metal plug being made of the same metal as the metal of the silicide layer. The metal plug may be a cobalt plug. The polysilicon gate and composite region may form part of the same device or different devices.
Still further, according to the invention, there is provided a semiconductor structure that includes at least two composite regions, and a silicide layer, wherein at least two of the composite regions are interconnected by means of a single metal plug contacting the at least two composite regions, the metal plug being made of the same metal as the metal of the silicide layer. The metal plug may be a cobalt plug. The composite regions may form part of the same device or different devices.
Still further, according to the invention, there is provide a semiconductor device comprising a polysilicon gate, a n+ composite defining a source region, a n+ composite defining a drain region, a plurality of polysilicon drain regions extending between a drain contact and the drain region, and a silicide layer, wherein at least one of the polysilicon drain regions is connected to the n+ drain composite by a metal plug made of the same material as the metal of the silicide layer. More than one polysilicon drain region may be connected to the n+ drain composite by means of one or more of said metal plugs. The metal plugs may be cobalt plugs.
REFERENCES:
patent: 4692349 (1987-09-01), Georgiou et al.
patent: 4793896 (1988-12-01), Douglas
patent: 2002/0132191 (2002-09-01), Chuang
Syd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr., “Handbook of Multilevel Metallization for Integrated Circuits,” Noyes Publ., Westwood, New Jersey (1993), pp. 42-44.
Hopper Peter J.
Johnson Peter
Lindorfer Philipp
Strachon Andy
Vashchenko Vladislav
Lee Eddie
Magee Thomas
National Semiconductor Corporation
Vollrath Jurgen
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