Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-02-19
2003-05-13
Nguyen, Viet Q. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S697000
Reexamination Certificate
active
06562713
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of replacing, etching, or doping the gate, or similar structure, of a semiconductor device using a planarizing silicon oxide or nitride layer to protect surrounding semiconductor areas while the old gate is exposed and processed.
2. Discussion of the Related Art
Typically, when a semiconductor device gate is to be removed, etched, or doped or subjected to some other processing, the surrounding source and drain regions and other sensitive areas are protected by laying down a layer of tetraethoxysilane, tetraethylorthosilicate, tetraethelorthosilicate, or tetrethoxysilicide, any of which is referred to in the semiconductor art as TEOS. After deposition of TEOS, it is necessary to planarize the TEOS layer down to the gate so as to expose the gate for subsequent processing. The planarizing of the TEOS layer is usually accomplished by chemical mechanical polishing (CMP). Aside from the disadvantage of having to perform a CMP operation, this process has other disadvantages. For one, CMP operations cause dishing in the TEOS substrate when the gates are spaced relatively far apart. Dishing can lead to shorts developing between the gates in a replacement gate process. The shorts can develop because of the remaining metal on top of the TEOS after metal CMP.
SUMMARY OF THE INVENTION
Disclosed is a method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma layer of a silicon compound, selected from the group silicon oxide and silicon nitride, in a manner effective in leaving an upper surface of said gate exposed.
In another aspect of the invention said deposition step further comprises depositing said silicon compound to a thickness substantially the same height of said gate, and the removal of any excess said silicon compound from atop said gate.
In another aspect of the invention said removal step further comprises depositing and patterning a resist layer to expose the top of said gate, etching away said excess silicon compound, and removing said resist layer.
In another aspect of the invention said depositing step is accomplished with a high density plasma chemical vapor deposition.
Disclosed is a method of processing short gates while protecting long gates on a semiconductor surface, the method comprising depositing a planarizing layer of a silicon compound, selected from the group silicon nitride and silicon oxide, up to substantially the same height as said gates, and processing said semiconductor surface.
In another aspect of the invention said deposition step is accomplished with a high density plasma chemical vapor deposition.
In another aspect of the invention said processing is a gate implant.
REFERENCES:
patent: 4502202 (1985-03-01), Malhi
patent: 4555843 (1985-12-01), Malhi
patent: 4564584 (1986-01-01), Fredericks et al.
patent: 4728617 (1988-03-01), Woo et al.
patent: 4745086 (1988-05-01), Parrillo et al.
patent: 5453389 (1995-09-01), Strain et al.
patent: 5472898 (1995-12-01), Hong et al.
patent: 5536669 (1996-07-01), Su et al.
patent: 5665621 (1997-09-01), Hong
patent: 5731239 (1998-03-01), Wong et al.
patent: 5828102 (1998-10-01), Bergemont
patent: 5856225 (1999-01-01), Lee et al.
patent: 5893739 (1999-04-01), Kadosh et al.
patent: 6008096 (1999-12-01), Gardner et al.
patent: 6060345 (2000-05-01), Hause et al.
patent: 6060358 (2000-05-01), Bracchitta et al.
patent: 6060364 (2000-05-01), Maszara et al.
patent: 6110818 (2000-08-01), Haskell
patent: 6117715 (2000-09-01), Ha
patent: 6133102 (2000-10-01), Wu
patent: 6156598 (2000-12-01), Zhou et al.
patent: 6239008 (2001-05-01), Yu et al.
patent: 6251731 (2001-06-01), Wu
patent: 6258677 (2001-07-01), Ang et al.
patent: 6277683 (2001-08-01), Pradeep et al.
patent: 6291278 (2001-09-01), Xiang et al.
patent: 6365523 (2002-04-01), Jang et al.
patent: 6368988 (2002-04-01), Li et al.
patent: 6410403 (2002-06-01), Wu
patent: 484128 (1992-05-01), None
patent: 06053507 (1994-02-01), None
patent: 06204213 (1994-07-01), None
patent: 06349765 (1994-12-01), None
patent: 09312397 (1997-12-01), None
Belyansky Michael P.
Dokumaci Omer H.
Doris Bruce B.
Hanafi Hussein I.
F.Chau & Associates, LLP
International Business Machines - Corporation
Nguyen Viet Q.
Nhu David
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