Method of protecting an alignment mark in a semiconductor manufa

Details Method of protecting an alignment mark in a semiconductor manufa Method of protecting an alignment mark in a semiconductor manufa

1997-04-25

1998-09-01

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438631, 438633, 438975, H01L 2128

Patent

active

058010904

ABSTRACT:
The present invention is a method of protecting an alignment mark in semiconductor manufacturing process with CMP. This invention utilizes a via mask or masking blade to remove the intermetal dielectric layer on a wide clear -out window using two etching steps. One etching step is performed before intermetal dielectric layer polish. The other etching step is performed after intermetal dielectric layer polish. Thus, there is no intermetal dielectric layer remained on the alignment mark and the alignment mark keeps the original shape.

REFERENCES:
patent: 4936930 (1990-06-01), Gruber et al.
patent: 5401691 (1995-03-01), Caldwell
patent: 5503962 (1996-04-01), Caldwell
patent: 5627110 (1997-05-01), Lee et al.

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