Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2005-06-28
2005-06-28
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S008000, C326S037000, C326S039000, C716S030000, C716S030000
Reexamination Certificate
active
06912601
ABSTRACT:
An apparatus comprising a wireless transceiver and a programmable logic circuit. The wireless transceiver may be coupled to the programmable logic circuit. The programmable logic circuit may comprise a programmable logic device, a processor, and a memory circuit, implemented in a single integrated circuit package.
REFERENCES:
patent: 4051352 (1977-09-01), Eichelberger et al.
patent: 4940909 (1990-07-01), Mulder et al.
patent: 5204663 (1993-04-01), Lee
patent: 5237699 (1993-08-01), Little et al.
patent: 5241224 (1993-08-01), Pedersen et al.
patent: 5268598 (1993-12-01), Pedersen et al.
patent: 5287017 (1994-02-01), Narasimhan et al.
patent: 5364108 (1994-11-01), Esnouf
patent: 5384499 (1995-01-01), Pedersen et al.
patent: 5386155 (1995-01-01), Steele et al.
patent: 5426744 (1995-06-01), Sawase et al.
patent: 5511211 (1996-04-01), Akao et al.
patent: 5548228 (1996-08-01), Madurawe
patent: 5548552 (1996-08-01), Madurawe
patent: 5550842 (1996-08-01), Tran
patent: 5557217 (1996-09-01), Pedersen et al.
patent: 5572148 (1996-11-01), Lytle et al.
patent: 5594367 (1997-01-01), Trimberger et al.
patent: 5598108 (1997-01-01), Pedersen
patent: 5603043 (1997-02-01), Taylor et al.
patent: 5608337 (1997-03-01), Hendricks et al.
patent: 5625563 (1997-04-01), Rostoker et al.
patent: 5752063 (1998-05-01), DeRoo et al.
patent: 5757207 (1998-05-01), Lytle et al.
patent: 5760607 (1998-06-01), Leeds et al.
patent: 5798656 (1998-08-01), Kean
patent: 5864486 (1999-01-01), Deming et al.
patent: 5990717 (1999-11-01), Partovi et al.
patent: 6005806 (1999-12-01), Madurawe et al.
patent: 6023570 (2000-02-01), Tang et al.
patent: 6025737 (2000-02-01), Patel et al.
patent: 6389321 (2002-05-01), Tang et al.
patent: 6401224 (2002-06-01), Schoniger et al.
patent: 6446242 (2002-09-01), Lien et al.
patent: 6448820 (2002-09-01), Wang et al.
patent: 420388 (1991-04-01), None
patent: 455414 (1991-11-01), None
patent: 510815 (1992-10-01), None
Microcontroller Acceleration, By Jesse Jenkins, 1993 IEEE, pp. 416-424.
A Family of User-Programmable Peripherals with a Functional Unit Architecture, By A.S. Shubat et al., 1992 IEEE, pp. 515-529.
A User-Programmable Peripherial With Functional Unit Architecture, By A. Shubat et al., pp. 23-24.
A 10ns, 4000 Gate, 160 Pin CMOS EPLD Developed on a 0.8um Process, By R. Patel et al., 1993 IEEE, pp. 7.6.1-7.6.5.
Obtaining 70MHz Performance in the MAX Architecture, By S. Kopec et al., May 1991, pp. 69-74.
SIPPOS (Single Poly Pure CMOS) EEPROM Embedded FPGA by News Ring Interconnection and Highway Path, By K. Ohsaki et al., 1994 IEEE, pp. 9.4.1-9.4.4.
Intel's FLEXlogic FPGA Architecture, By D.E. Smith, 1993 IEEE, pp. 378-384.
Dual and Fail-Safe Redundancy for Static Mask-ROMs and PLAs, By N. Tsuda, 1993 IEEE, pp. 57-66.
A 0.5um Technology for Advanced Microcontroller Applications, By U. Shama et al., 1994 IEEE, pp. 67-68.
A Large Scale FPGA with 10K Core Cells with CMOS 08.um 3-Layered Metal Process, By H. Muroga et al., 1991 IEEE, pp. 6.4.1-6.4.4.
Session 15: High-Speed Digital Circuits, FAM 15.5: A 9ns, Low Standby Power CMOS PLD with a Single-Poly EPROM Cell, By S. Frake et al., Feb. 17, 1989, pp. 344-346.
A Microcontroller Embedded with 4Kbit Ferroelectric Non-Volatile Memory, By T. Fukushima et al., 1996 IEEE, pp. 46-47.
Integrated Circuits for Smart Cards, By Julie Krueger, Oct. 9-12, 1995, pp. 1168-1170.
1.5V High Speed Read Operation and Low Power Consumption Circuit Technology for EPROM and Flash-EERPOM, By O. Matsumoto et al., 1993 IEEE, pp. 25.4.1-25.4.4.
Integrated Memory Elements on Microcontroller Devices, By Charles Melear, pp. 507-514.
Analog Counterparts of FPGAs Ease System Design, By F. Goodenough, Oct. 14, 1994, pp. 63-72.
PSD301 Programmable Peripheral With Memory for Microcontroller and Embedded Microprocessor Applications, by Chris Jay, 1991.
Single Chip Microcontroller with Internal EPROMs, By M. Yamamoto et al., National Technical Report, vol. 36, No. 3, Jun. 1990, pp. 295-302.
Cypress Semiconductor Corp.
Gaffin Jeffrey
Maiorana PC Christopher P.
Nguyen Mike
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