Method of programming for programmable circuit in redundancy cir

Details Method of programming for programmable circuit in redundancy cir Method of programming for programmable circuit in redundancy cir

1983-12-20

1986-12-16

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

365240, 371 10, 371 21, G11C 2900, G06F 1100

Patent

active

046302417

ABSTRACT:
A method of programming for a programmable circuit in a redundancy circuit system including a RAM having normal and spare memory cell rows constructed on a common chip and the programmable circuit, is disclosed. The programmable circuit has a plurality of fuses and can produce a signal for disabling all the normal memory cell rows while enabling a spare memory cell row corresponding to a combination of blown-out fuses and non-blown-out ones among the plurality of fuses with respect to a certain normal memory cell row address. The method comprises the steps of detecting a faulty memory cell row, storing the address thereof and supplying a fuse-blowing current one after another of those of the programmable circuit fuses which correspond to a certain logic level bits of the stored address.

REFERENCES:
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patent: 4358833 (1982-11-01), Folmsbee et al.
patent: 4446534 (1984-05-01), Smith
patent: 4460998 (1984-07-01), Yamada et al.
patent: 4464736 (1984-08-01), Smith
Tolley et al, "72K RAM Stands Up to Soft and Hard Errors", Electronics, vol. 55, No. 12, Jun. 16, 1982, pp. 147-151.
Spaw et al, "A 128K EPROM With Redundancy", IEEE Solid State Circuits Conference, Digest of Technical Papers, Feb. 1982, pp. 112-113, 304.
IEEE International Solid-State Circuits Conference, 1981, pp. 80-81, "Memories and Redundancy Techniques", K. Kokkonen et al.

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