Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-05
2003-09-16
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S195000
Reexamination Certificate
active
06621736
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of programming a split-gate flash memory cell and, more particularly, to a method of programming a split-gate flash memory cell with a positive inhibiting word line voltage.
2. Description of the Related Art
A non-volatile memory cell is a memory cell that retains data stored in the cell after power has been removed from the cell. One type of non-volatile memory cell is a split-gate flash memory cell. A split-gate flash memory cell, also known as a transistor and a half memory cell, integrates a memory transistor and an access transistor.
FIG. 1
shows a cross-sectional diagram that illustrates a prior art split-gate flash memory cell
100
. As shown in
FIG. 1
, memory cell
100
, which is formed in a p-type semiconductor substrate
110
, includes a n++ source region
112
that is formed in substrate
110
, and a n+ drain region
114
that is formed in substrate
110
a distance apart-from source region
112
.
As further shown in
FIG. 1
, memory cell
100
also includes a channel region
116
that is located between source and drain regions
112
and
114
. Channel region
116
, in turn, includes a source-side channel region
116
A, a drain-side channel region
116
B, and an intermediate channel region
116
C connected to source-side channel region
116
A and a drain-side channel region
116
B.
In addition, memory cell
100
includes a layer of gate oxide
120
that is formed over channel region
116
, and a polysilicon floating gate
122
that is formed on gate oxide layer
120
over source region
112
and source-side channel region
116
A. Floating gate
122
, in turn, has a tip
124
that is located at the outer edge of floating gate
122
.
Further, memory cell
100
includes a layer of interpoly dielectric
126
that is formed on gate oxide layer
120
and the side wall of floating gate
122
over intermediate channel region
116
C, and over floating gate
122
. Cell
100
additionally includes a polysilicon control gate
130
that is formed on gate oxide layer
120
over the drain-side channel region
116
B, and on interpoly dielectric layer
126
over intermediate channel region
116
C, floating gate
122
, and source-side channel region
116
A.
In operation, cell
100
is read by placing ground on source region
112
, a positive drain voltage on drain region
114
, and a read voltage on control gate
130
. Under these conditions, when cell
100
is unprogrammed, the read voltage is sufficient to invert channel region
116
and allow a current to flow from drain region
114
to source region
112
. The presence of current, in turn, is interpreted to be a first logic state.
On the other hand, when cell
100
is programmed, the read voltage is insufficient to invert source-side channel region
116
A, thereby preventing a current from flowing from drain region
114
to source region
112
. In this case, the absence of current is interpreted to be a second logic state.
In addition to reading, cell
100
is erased by placing ground on substrate
110
, source region
112
, and drain region
114
. In addition, an erase voltage is placed on control gate
130
. The erase voltage can be, for example, 10V These voltages set up an electric field from floating gate
122
to control gate
130
across interpoly dielectric layer
126
.
Tip
124
, in turn, intensifies the electric field across interpoly dielectric layer
126
. Thus, under the influence of the intensified electric field, the electrons on floating gate
122
tunnel through interpoly dielectric layer
126
from tip
124
to control gate
130
via the well known Fowler-Nordheim mechanism.
One of the advantages of cell
100
is that, as a result of the intensification of the electric field, lower voltages can be applied to cell
100
to achieve erasure than are required for other types of cells. The amount of intensification provided by tip
124
is largely a factor of the shape of tip
124
.
In addition to reading and erasing, cell
100
is programmed by placing a source voltage, such as 10 volts, on source region
112
, and a drain voltage, such as 1V, on drain region
114
. In addition, a control gate voltage which is at least a threshold voltage greater than the drain voltage is placed on control gate
130
. For example, when 1V is placed on drain region
114
, approximately 1.7V can be placed on control gate
130
.
The control gate voltage on control gate
130
attracts electrons to the surface of channel region
116
. The voltage difference between source region
112
and drain region
114
sets up an electric field. The presence of sufficient electrons at the surface of channel region
116
allows electrons to flow from drain region
114
to source region
112
along the surface of channel region
116
under the influence of the electric field.
The electric field intensifies in the intermediate channel region
116
C. The electrons are accelerated by the intensified electric field into having ionizing collisions with the lattice which, in turn, generate hot electrons. The hot electrons have additional collisions with the lattice producing additional hot electrons to form a hot electron programming current.
A number of the hot electrons penetrate gate oxide layer
120
and accumulate on floating gate
122
, thereby programming the cell. When cell
100
is read, the negative charge on floating gate
122
from the accumulated electrons prevents the read voltage from inverting source-side channel region
116
A.
FIG. 2
shows a schematic diagram that illustrates a prior art, split-gate memory array
200
. As shown in
FIG. 2
, array
200
includes a -plurality of split-gate memory cells
100
that are arranged in rows and columns. In addition, array
200
includes a plurality of source lines SL
1
-SLn that are formed such that each source line SL is connected to each source region
112
in two adjacent rows of cells
100
.
Array
200
also includes a plurality of bit lines BL
1
-BLm that are formed such that each bit line BL is connected to each drain region
114
in a column of drain regions
114
. Further, array
200
includes a plurality of word lines WL
1
-WLs that are formed such that each word line WL is connected to each control gate
130
in a row of memory cells
100
.
In operation, when the memory cells
100
in a row of cells in array
200
are to be programmed, a source voltage, such as 10 volts, is placed on the source line SL that is connected to the to-be-programmed memory cells. In addition, ground is placed on the remaining source lines SL. For example, if memory cells in the first row are to be programmed, the source voltage is placed on source line SL
1
while ground is placed on the remaining source lines SLn.
Further, a first bit voltage, such as 1V, is placed on each bit line BL that is connected to a to-be-programmed memory cell
100
. In addition, an second bit voltage, such as 2.5 volts, is placed on each bit line BL that is connected to a not to-be-programmed memory cell
100
. For example, if cell A is to be programmed and cell C is not to be programmed, then 1V is placed on bit line BL
1
, while 2.5V are placed on bit line BL
2
.
In addition, a programming voltage, such as 1.7V, is placed on the word line WL that is connected to the to-be-programmed memory cells. Ground, in turn, is placed on the remaining word lines WL. For example, if the first row of cells is to be programmed, the programming voltage is placed on word line WL
1
, while ground is placed on word lines WL
2
-WLs. Further, ground is placed on substrate
110
. Under these programming conditions, each to-be-programmed cell
100
in the first row of cells is programmed.
One problem with array
200
is that when the memory cells in one row of cells are programmed, cells in an adjacent row of cells are undesirably programmed over time. As shown in
FIG. 2
when cell A is programmed, cell B experiences the same source and bit voltages as cell A. Similarly, cell D shares the same source and bit voltages as cell C, and the sam
Mirgorodski Yuri
Poplevine Pavel
Poulter Mark W.
Dinh Son T.
National Semiconductor Corporation
Pickering Mark C.
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