Method of programming a multi-level, electrically...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185030, C365S185190

Reexamination Certificate

active

07110300

ABSTRACT:
A method of programming a multi-level, electrically-programmable memory with memory cells electrically programmable into at least two distinct programmed states, includes: defining at least two programming sequences, each one being designed for bringing memory cells into at least one respective programmed state; receiving a pattern of data to be written into a selected group of memory cells of the memory; analyzing the pattern for determining sub-groups of memory cells, each sub-group of memory cells including the memory cells in the selected group that are to be brought into at least a respective one of the at least two programmed states; and submitting the memory cells in each sub-group to the respective programming sequence. A memory circuit and a computing system are also provided.

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patent: WO 01/63613 (2001-08-01), None
Roberto Versari et al., “Optimized Programming of Multilevel Flash Eeproms”, ICECS 2001: 8thIEEE International Conference on Electronics, Circuits and Systems, vol. 2, Sep. 2, 2001, pp. 945-948, XP010563149.
David Esseni et al., Trading-Off Programming Speed and Current Absorption in Flash Memories with the Ramped-Gate Programming Technique, IEEE Transactions on Electron Devices, vol. 47, No. 4, Apr. 2000, pp. 828-834, XP001131051.
European Search Report dated Jul. 25, 2003 for European Application No. 03425096.9.

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