Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-05-24
2005-05-24
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185010
Reexamination Certificate
active
06898126
ABSTRACT:
A method of programming a flash memory through boosting a voltage level of a source line. The flash memory has n memory cell transistors cascaded in series, a local bit line positioned above the n memory cell transistors, a buried bit line positioned under the n memory cell transistors, and a source line positioned under the buried bit line. The method includes inputting a word line voltage to a control gate of a kthmemory cell transistor, and after floating the local bit line, inputting a source line voltage to the source line for inducing an FN tunneling effect inside the kthmemory cell transistor through capacitance coupling between the buried bit line and the source line.
REFERENCES:
patent: 6064592 (2000-05-01), Nakagawa et al.
Chang Hsiang-Chung
Wong Wei-Zhe
Yang Ching-Sung
Hsu Winston
Le Thong Q.
Powerchip Semiconductor Corp.
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