Method of programming a desired source resistance for a driver s

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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326 86, 326 33, 326 34, H03K 190948, H03K 1714, H03K 19003

Patent

active

055811973

ABSTRACT:
The output impedance in a CMOS output driver stage is programmed and compensated by complementary current mirrors that are MOS devices in series with each of the conventional pull-up and pull-down devices. The conduction of these additional complementary devices is controlled according to complementary programming signals that are compensated for variations in manufacturing process parameters as well as for changes in temperature. A P-type programming signal may be referenced to +VDD and be produced from an N-type programming signal referenced to GND by the action of a gate voltage mirror that includes symmetrical N-type and P-type FET's in series. The N-type programming signal may be produced in the first instance from the gate voltage of an N-type FET used in a feedback loop that servos an external programming voltage to track an internally generated reference voltage. That gate voltage exhibits variations that reflect differences attributable to both process variations and to temperature. Those exhibited variations are communicated by a current mirror to a gate voltage mirror that produces the complementary programming signals, and which themselves constitute negative feedback. The complementary current mirrors are of known of gain, which in conjunction with knowing the value of VDD, allows the determination in advance of a definite table of programming resistance values versus output impedances.

REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 5081380 (1992-01-01), Chen
patent: 5124580 (1992-06-01), Matthews et al.
patent: 5235222 (1993-08-01), Kondoh et al.

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