Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-06-05
2007-06-05
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C029S852000
Reexamination Certificate
active
11396203
ABSTRACT:
A method of production of a circuit board utilizing electroplating which prevents signal reflection and noise due to unnecessary parts in the circuit patterns when electroplating to form circuit patterns on the board to thereby improve the electrical properties and realize higher density layout of the circuit patterns, including the steps of forming a first electroless plating layer and an overlying first plating resist on a metal foil-clad insulating board, feeding power to the first electroless plating layer to form a first electroplating layer over the first electroless plating layer in resist openings; removing the first plating resist; removing the exposed first electroless plating layer and metal foil to expose the insulating board; forming a second electroless plating layer over the exposed parts of the board and the circuit patterns; forming a second plating resist over that; removing the second electroless plating layer at the resist openings; feeding power to the second electroless plating layer under the second plating resist to form a second electroplating layer over the circuit patterns in the resist openings; removing the second plating resist; and removing the exposed second electroless plating layer.
REFERENCES:
patent: 6852625 (2005-02-01), Shin et al.
patent: 2005/0039948 (2005-02-01), Asai et al.
patent: 2005/0121229 (2005-06-01), Takai et al.
patent: 2000-114412 (2000-04-01), None
patent: 2000114412 (2000-04-01), None
Okazawa Hideyasu
Takeda Yoshiki
Coleman W. David
Lee Jae
Morgan & Finnegan , LLP
Shinko Electric Industries Co. Ltd.
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