Method of producing relief structures for integrated semiconduct

Details Method of producing relief structures for integrated semiconduct Method of producing relief structures for integrated semiconduct

1981-07-16

1983-09-20

Newsome, John H.

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Radiation sensitive composition or product or process of making

427 431, 430299, B05D 306

Patent

active

044057075

ABSTRACT:
Relief structures comprised of double lacquer layers on substrates already having relief structures for integrated semiconductor circuits are produced by applying a lower lacquer layer onto such substrate and which is composed of a material which does not cross-link or decompose due to radiation energy and which has only relatively slight sensitivity at the radiation energy dosage range utilized for structuring; applying an upper lacquer layer onto the lower lacquer layer and which upper layer is thinner relative to the thickness of the lower layer by a factor of at least 2 and is composed of a highly sensitive negative lacquer material; generating desired relief structures in the upper lacquer layer and removing those portions of the lower lacquer which are not covered by the upper negative lacquer layer.

REFERENCES:
patent: 4004044 (1977-01-01), Franco et al.
patent: 4024293 (1977-05-01), Hatzakis
patent: 4202914 (1980-05-01), Havas et al.
patent: 4204009 (1980-05-01), Feng et al.
patent: 4268601 (1981-05-01), Namiki et al.
patent: 4287297 (1981-09-01), Ishihara et al.

Affiliated with

Also associated with

Rating

Method of producing relief structures for integrated semiconduct does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of producing relief structures for integrated semiconduct, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of producing relief structures for integrated semiconduct will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-588584