Method of producing polysilicon structure in the 1 .mu.m range o

Details Method of producing polysilicon structure in the 1 .mu.m range o Method of producing polysilicon structure in the 1 .mu.m range o

1982-01-21

1983-04-19

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156657, 1566591, 156345, 204192E, 252 791, H01L 21306

Patent

active

043804896

ABSTRACT:
Polysilicon structures down to a 1 .mu.m range on substrates containing integrated semiconductor circuits are produced by plasma etching in a plate reactor with the use of SF.sub.6 and an inert gas as the reactive gas. During this process, a semiconductor crystal wafers (4, 17) covered with a SiO.sub.2 layer (16) and a polysilicon layer (15) is provided with an etch mask (14) and positioned on a grounded electrode of the plate reactor and an etching process, which achieves a high selectivity of polysilicon (15) to SiO.sub.2 (16) and to the etch mask (14), is carried out with a HF power, P, of <0.1 watt/cm.sup.2, a gas pressure, p, ranging from 60 to 120 Pa, and an electrode temperature ranging from 20.degree. to 60.degree. C. With the inventive process, large scale integrated semiconductor circuits are produced in a single stage sequence with high etching selectivity, uniform etching and a high throughput of silicon wafers.

REFERENCES:
patent: 4208241 (1980-06-01), Harshbarger et al.
patent: 4214946 (1980-07-01), Forget et al.
H. Mader, "Anisotropic Plasma Etching of Polysilicon with CF.sub.4 ", ECS Spring Meeting (1980) pp. 274-276.
C. J. Mogob et al., "Anisotropic Plasma Etching of Polysilicon", J. Voc. Sci. Technol., vol. 17 (May/Jun. 1980), pp. 721-730.
R. A. Gdula, "SF.sub.6 RIE of Polysilicon", ECS Fall Meeting (1979) pp. 1524-1526.
N. Endo et al., "1 .mu.m MOS Process Using Inisotropic Dry Etching", IEEE Trans-Actions on Electron Devices, vol. ED-27 (Aug., 1980) pp. 1346-1351.

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