Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-03-08
2005-03-08
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
73, 73, 73, C216S067000
Reexamination Certificate
active
06864182
ABSTRACT:
Based upon an existing or to be produced multi-layered semiconductor-insulator-semiconductor carrier layer wafer (SOI substrate), irregularity of the etching conditions between the center and the edge region occurring during dry etching can be counteracted by a number of alternative steps, in particular, an additional layer construction compensating for the etching irregularity so that in any event an approximately homogeneous etching removal takes place over the entire area of the wafer to be etched.
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patent: 5972794 (1999-10-01), Katakura
patent: 6124063 (2000-09-01), Dauksher et al.
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patent: 6555297 (2003-04-01), Lercel
patent: WO 9949365 (1999-09-01), None
Butschke Jörg
Ehrmann Albrecht
Kragler Karl
Letzkus Florian
Reuter Christian
Greenberg Laurence A.
Mayback Gregory L.
Norton Nadine G.
Stemer Werner H.
Umez-Eronini Lynette T.
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