Method of producing interconnections in a semiconductor integrat

Details Method of producing interconnections in a semiconductor integrat Method of producing interconnections in a semiconductor integrat

1984-12-31

1987-09-15

Bashore, S. Leon

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156651, 1566591, B23P 1500, B23P 2506

Patent

active

046937838

ABSTRACT:
Method of producing metal interconnections in a semiconductor integrated circuit structure of a body of silicon coated with silicon dioxide having openings therein exposing contact regions to underlying silicon. A thick layer of an insulating or dielectric material, for example, polymide, is deposited on the body. Grooves in the pattern of the desired interconnections are etched through the thick insulating layer to the underlying silicon dioxide and contact regions. Metal is deposited to fill the grooves and cover the thick layer of insulating material. Excess metal is removed to form a planar surface exposing the surface of the thick insulating layer with the grooves containing metal to provide electrical connections between contact regions.

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patent: 4381341 (1983-04-01), Przybysz et al.
patent: 4472240 (1984-09-01), Kameyama
patent: 4518629 (1985-05-01), Jeuch
patent: 4526631 (1985-07-01), Silvestri et al.
patent: 4528065 (1985-07-01), Yamazaki
patent: 4544441 (1985-10-01), Hartmann et al.
patent: 4550353 (1985-10-01), Hirai et al.
patent: 4582563 (1986-04-01), Hazuki et al.

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