Method of producing high dielectric insulator for integrated...

Details Method of producing high dielectric insulator for integrated... Method of producing high dielectric insulator for integrated...

2002-10-09

2003-09-23

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S287000, C438S591000

Reexamination Certificate

active

06624093

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit fabrication techniques and specifically to a method of producing an insulating layer on an integrated circuit for structures such as insulated gate field effect transistors (IGFET).
Integrated circuits produced on silicon wafers make use of silicon dioxide (SiO
2
) as an insulator between conductors including interconnections between circuit elements, capacitor plates, and the gate contact and the current carrying channel (the “transistor channel”) separating drain and source contacts.
With the continued miniaturization of circuit elements in ultra-large scale integrated (ULSI circuits), the thickness of the SiO
2
layer that forms the insulator in an IGFET must be decreased so as to offset the reduction in area of the gate contact while preserving the necessary capacitive coupling. Although improvements in SiO
2
processing have allowed high quality SiO
2
layers of the required thickness to be produced to date, a fundamental thickness limitation looms for gate oxides thinner than approximately 12 Å. At this thickness, electron tunneling is expected to provide current leakage that is unacceptably high even for high performance devices and much too high for increasingly popular low power devices.
Electron tunneling could be prevented if a material having a higher dielectric constant (&kgr;) than SiO
2
could be found to serve as the insulation on the gate. With such a high &kgr; insulator, the gate insulation could be made physically thicker for a given capacitance dramatically reducing the tunneling.
Potential materials for producing a high &kgr; electrical insulator must produce an electrical interface with the silicon having few fixed charges or recombination centers to not limit carrier mobility in the transistor channel. The material should readily adopt an amorphous phase to reduce electrical leakage and doping diffusion along grain boundaries. Further, the material must not be prone to reactions with the silicon substrate that would cause formation of an interfacial SiO
2
layer. This latter interfacial SiO
2
layer acts to reduce the capacitance of the high &kgr; material by adding a small series capacitance lowering the overall capacitance according to standard series additions of capacitance.
Zirconium (Zr) and hafnium (Hf) compounds have been investigated as high &kgr; materials for integrated circuit application. Oxides of both elements have high dielectric constants (approximately 25) and can form stable silicate phases (MSi
x
O
y
) M═Hf or Zr) and appear to be stable in contact with silicon at temperatures approaching required integrated circuit processing temperatures. It appears that a relatively small amount of Hf or Zr can significantly increase dielectric constants and that deleterious hafnium-silicon or zirconium-silicon bonds will be energetically unfavorable compared to silicon-oxygen bonds at the interface to the silicon substrate.
Previous attempts to grow hafnium-silicate or hafnium-oxide have used electron beam evaporation of hafnium-silicate onto a bare silicon substrate, sputter deposition of hafnium-silicate onto a bare silicon substrate, or chemical vapor deposition (CVD) of hafnium-oxide or hafnium-silicate on bare silicon substrate.
BRIEF SUMMARY OF THE INVENTION
The electrical and mechanical qualities of the silicon-SiO
2
interface are extremely important in the production of semiconductor devices. The present inventors believe that removing the SiO
2
layer from the silicon substrate, required in the prior art deposition of hafnium silicate, may result in contamination of the silicon surface, especially in the moderate vacuum levels found in deposition chambers or CVD reactors. This contamination can result in an unwanted, thin SiO
2
layer and/or a poor quality silicate layer.
Accordingly, the present invention creates a hafnium-silicate layer without removal of the SiO
2
layer, depositing hafnium directly on the SiO
2
layer then heating the substrate to promote a solid state reaction producing hafnium-silicate and consuming the underlying SiO
2
.
Specifically, the present invention provides a method for the manufacture of hafnium-silicate film including the steps of depositing hafnium on the silicon dioxide layer of a silicate substrate and heating the substrate to react the deposited hafnium with the silicon dioxide layer to form a corresponding layer of hafnium-silicate.
Thus, it is one object of the invention to provide a method of producing a hafnium-silicate layer that does not require removal of a protecting silicon dioxide layer from the substrate.
The reaction step may continue until the silicon dioxide-between the hafnium-silicate and the silicon substrate is substantially removed or the hafnium has fully reacted with all silicon dioxide between the hafnium-silicate and the silicon substrate.
Thus, it is another object of the invention to provide method of producing a hafnium-silicate layer that is in direct contact with the silicon without an intervening and capacitance-decreasing layer of silicon dioxide.
The deposition of hafnium may be performed by electron beam evaporation.
Thus, it is another object of the invention to provide a method of depositing hafnium on the silicon dioxide that avoids the ion damage, for example, attendant to sputter deposition.
The foregoing and other objects and advantages of the invention will appear from the following description. In this description, reference is made to the accompanying drawings, which form a part hereof, and in which there is shown by way of illustration, a preferred embodiment of the invention. Such embodiment and its particular objects and advantages do not define the scope of the invention, however, and reference must be made therefore to the claims for interpreting the scope of the invention.


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Wilk, G. D. et al., “Electrical Properties of Hafnium Silicate Gate Dielectrics Deposited Directly on Silicon, Applied Physics Letters”, vol., No. 19, May 10, 1999.
Wilk, G. D. et al., “High-k Gate Dielectrics: Current Status and Materials Properties Considerations”, Journal of Applied Physics, vol. 89, No. 10, May 15, 2001.

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