Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-03-06
2004-11-02
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S047000, C438S166000
Reexamination Certificate
active
06812071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, a method of producing the semiconductor device, a liquid crystal display device, and a method of producing the liquid crystal display device, and more specifically, to a semiconductor device that achieves high reliability, a method of producing the semiconductor device, a liquid crystal display device, and a method of producing the liquid crystal display device.
2. Description of the Background Art
Conventionally, a liquid crystal display device utilizing a thin film field-effect transistor is known to be one type of a liquid crystal display device. A glass substrate on which the thin film field-effect transistor is formed in such a liquid crystal display device is shown in FIG.
38
.
FIG. 38
is a schematic cross sectional view showing a conventional liquid crystal display device. The liquid crystal display device will be described with reference to FIG.
38
.
As shown in
FIG. 38
, an n-type thin film field-effect transistor
119
and a p-type thin film field-effect transistor
120
are formed in a drive circuit region on a glass substrate
101
of the liquid crystal display device. In addition, a capacitance
121
and a thin film field-effect transistor for a pixel
122
are formed in a display pixel region.
An underlying film
102
is formed on glass substrate
101
in the drive circuit region. A silicon oxide film is used as the underlying film. On underlying film
102
, n+ type impurity regions
103
a
,
103
b
, n− type impurity regions
104
a
,
104
b
, and a channel region
106
a
are formed using the same semiconductor film. An insulating film
107
serving as a gate insulating film is formed on channel region
106
a
. A gate electrode
108
a
is formed on gate insulating film
107
. N+ type impurity regions
103
a
,
103
b
and n− type impurity regions
104
a
,
104
b
form source/drain regions. N+ type impurity regions
103
a
,
103
b
, n− type impurity regions
104
a
,
104
b
, channel region
106
a
, insulating film
107
located on channel region
106
a
, and gate electrode
108
a
formed an n-type thin film field-effect transistor
119
.
In addition, on underlying film
102
, p-type impurity regions
105
a
,
105
b
and a channel region
106
b
are formed using the same semiconductor film. Insulating film
107
serving as a gate insulating film is formed on channel region
106
b
. A gate electrode
108
b
is formed on insulating film
107
in the region located above channel region
106
b
. P-type impurity regions
105
a
,
105
b
, channel region
106
b
, insulating film
107
serving as the gate insulating film, and gate electrode
108
b
form a p-type thin film field-effect transistor
120
. An interlayer insulating film
110
is formed on n-type thin film field-effect transistor
119
and p-type thin film field-effect transistor
120
. Contact holes
111
a
to
111
d
are formed in regions located above n+ type impurity regions
103
a
,
103
b
and p-type impurity regions
105
a
,
105
b
by removing parts of interlayer insulating film
110
and insulating film
107
. Metal interconnections
112
a
to
112
d
are formed such that they extend from inside contact holes
111
a
to
111
d
onto an upper surface of interlayer insulating film
110
. A passivation film (not shown) is formed on metal interconnections
112
a
to
112
d
. A planarized film
113
is formed on the passivation film.
In the display pixel region, a capacitance electrode
109
is formed on underlying film
102
. Another capacitance electrode
108
e
is formed on capacitance electrode
109
with insulating film
107
that serves as a dielectric film existing therebetween. Capacitance electrodes
109
,
108
e
and insulating film
107
form capacitance
121
. An n+ type impurity region
103
c
serving as a conductive region is formed on underlying film
102
adjacent to capacitance electrode
109
.
Moreover, on underlying film
102
, n+ type impurity regions
103
d
to
103
f
, n− type impurity regions
104
d
to
104
g
, and channel regions
106
c
,
106
d
are formed using the same semiconductor film. Gate electrodes
108
c
,
108
d
are formed on channel regions
106
c
,
106
d
with insulating film
107
serving as a gate insulating film existing therebetween. Thus, n+ type impurity regions
103
d
,
103
e
, n− type impurity regions
104
d
,
104
e
, channel region
106
c
, insulating film
107
serving as the gate insulating film, and gate electrode
108
c
form one thin film field-effect transistor. In addition, n+ type impurity regions
103
e
,
103
f
, n− type impurity regions
104
f
,
104
g
, channel region
106
d
, insulating film
107
serving as the gate insulating film, and gate electrode
108
d
form another thin film field-effect transistor. Thin film field-effect transistor for a pixel
122
includes these two thin film field-effect transistors.
Interlayer insulating film
110
is formed on capacitance
121
and thin film field-effect transistor for a pixel
122
. Contact holes
111
e
to
111
g
are formed in regions located above n+ type impurity regions
103
c
,
103
d
,
103
f
by removing parts of interlayer insulating film
110
and insulating film
107
. Metal interconnections
112
e
,
112
f
are formed such that they extend from inside contact holes
111
e
to
111
g
onto an upper surface of interlayer insulating film
110
. A passivation film (not shown) is formed on metal interconnections
112
e
,
112
f
. Planarized film
113
is formed on the passivation film. A contact hole
114
is formed in planarized film
113
and the passivation film in the region located above metal interconnection
112
e
. A pixel electrode
115
using ITO (Indium Tin Oxide) and the like is formed such that it extends from inside contact hole
114
onto an upper surface of planarized film
113
.
FIGS. 39
to
42
are schematic cross sectional views related to the description of a method of producing the liquid crystal display device shown in FIG.
38
. The method of producing the liquid crystal display device will be described with reference to
FIGS. 39
to
42
.
First, underlying film
102
such as a silicon oxide film is formed on glass substrate
101
. An amorphous silicon film
126
is formed on underlying film
102
. Thus, the structure as the one shown in
FIG. 39
can be obtained.
Then, amorphous silicon film
126
is annealed using a laser or the like to produce a polysilicon film
128
. As a result, a structure such as the one shown in
FIG. 40
is obtained.
Then, a resist film (not shown) is formed on polysilicon film
128
. The resist film is subjected to exposure and development processes so as to form a channel pattern. Then, polysilicon film
128
is partially removed by etching using as a mask the resist film in which the channel pattern is formed so as to form polysilicon film
129
a
to
129
d
(see FIG.
41
). Thereafter, the resist film is removed. Thus, the structure as the one shown in
FIG. 41
is obtained.
Then, as shown in
FIG. 42
, a resist film
130
is formed in a region other than the region in which polysilicon film
129
c
is formed. Conductive impurities are implanted into polysilicon film
129
c
that is to become a capacitance electrode using resist film
130
as a mask to form capacitance electrode
109
. Phosphorus ions
131
are used as the conductive impurities to be implanted at this time. Thereafter, resist film
130
is removed.
Then, insulating film
107
(see
FIG. 38
) is formed on polysilicon film
129
a
,
129
b
,
129
d
and capacitance electrode
109
. A conductor film is formed on insulating film
107
. A resist film is formed on this conductor film. The resist film is subjected to exposure and development processes so as to form a gate pattern. The conductive film is partially removed by etching using as a mask the resist film in which this gate pattern is formed so as to form gate electrodes
108
a
to
108
d
(see
FIG. 38
) and a capacitance ele
Hayashi Masami
Kobayashi Masanao
Ghyka Alexander
Leydig , Voit & Mayer, Ltd.
Renesas Technology Corp.
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