Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2001-07-12
2002-09-17
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S406000, C438S422000, C438S456000, C438S475000
Reexamination Certificate
active
06451668
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of producing calibration structures in semiconductor substrates in the manufacture of components, particularly the production of micro-mechanical systems with integrated electronic semiconductor systems. The inventive method offers particular advantages in the application of photo-litho-graphic techniques in the processing of silicon wafers.
In the production of semiconductor components or sensor systems including micro-electronic and micro-mechanical components several layers or strata of different functions are, as a rule, superimposed and structured on a semiconductor wafer. For the proper operation of the later component it is necessary that the structures of the individual layers present a predetermined position relative to the respective structures underneath. The layers are, as a rule, structured by means of a litho-graphic technique in which the applied exposure equipment such as steppers or contact exposure devices, with the corresponding masks are precisely positioned relative to the layer or existing structure to be exposed. Adjustment or calibration markers are used for positioning. The creation of these calibration markers or structures is the subject matter of the present invention.
A preferred field of application of the inventive method is the production of micro-electronically integrated sensors or actuators. Micro-electronically integrated sensors measure a physical or chemical condition in the environment and process it to generate an electrical signal. Micro-electronically integrated actuators convert an electrical signal into a mechanical movement or an acoustic signal.
A pressure sensor should be quoted here as an example, wherein a silicon layer over a cavity serves as membrane on the principle of a box-type barometer or barometric cell. Examples of pressure sensors and their production are known from the German Patent DE 37 43 080 A1. An integrated transducer detects the movement or the bending condition of the membrane and provides a corresponding electrical signal. These sensors, which present a cavity under a semiconductor layer, are also suitable for the highly responsive measurement of temperature, radiation, mechanical movement (vibration, sound, acceleration and rotation) as well as of the dynamic or chemical properties (such as fluidity, viscosity, flow rate, pH level, electrochemical potential) of the surrounding medium.
Like in the case of an exemplary pressure sensor, the cavity under the membrane may be evacuated or contain an optional medium, i.e. a gas, a liquids or a solid material, as far as this medium is compatible with the manufacturing technology to be applied, specifically the high temperatures occurring in such manufacture.
The membrane consists in many cases of a mono-crystalline silicon layer because its physical properties can be reproduced very well and are known. The silicon layer may be a mono-crystalline or a deposited and re-crystallised silicon layer. For special applications the membrane may also consist of other forms of silicon, such as amorphous or poly silicon, of another semiconductor material such as germanium, gallium arsenide or other Ill-V semiconductors, or an isolator such as silicon dioxide, silicon nitride, tantalum oxide or titanium nitride, as far as these substances are compatible with the technology to be applied.
The transducer for detection of the bending condition of the membrane is composed, for instance, of an array of piezo-resistive resistors converting the mechanical strain in the silicon membrane, which results from bending, into electrical signals. These signals can be amplified, processed, compensated for interfering influences, converted into analog or digital signals and processed by a micro-electronic circuit produced in the same silicon layer. The transducers may also consist of wire strain gauges, piezo-electric, capacitive or chemo-electrical converters. The circuit and the transducers may be manufactured in an appropriate micro-electronic technology (bi-polar, BICMOS, CMOS, etc.), depending on the respective application.
In the production of such a sensor, which is composed of different layers or planes, in CMOS technique, first of all the first plane is exposed in a non-calibrated form because the process starts with blank silicon wafers. The exposure equipment, e.g. a stepper or contact exposure device, is here only roughly oriented in the range of +/−100 &mgr;m by mechanically striking against the edges of the wafer. All following planes are calibrated directly or indirectly with a high precision relative to this first plane. In a semiconductor process operating on structure sizes of 0.8 &mgr;m this calibration must be performed, for example, with a precision of +/−0.3 &mgr;m. In order to be able to utilize the precision of the stepper also for the positioning of the transducers relative to the cavities it is necessary that calibration markers can bee detected for the stepper during the exposure of the first CMOS plane, which markers were generated before in the definition of the cavities. The application of the calibration markers serves the purpose of positioning the transducers with the accuracy common in CMOS processes. Simulation calculations by the FEM method have furnished the resuit that with this precision the distribution of the electrical output signals remains below 2% of the measured value. The remaining distribution due to manufacture may be compensated by a logic circuit integrated into the chip.
For the production of the cavities underneath the membrane it is possible, for instance, to deposit a thin oxide layer on a wafer. Large-area recesses are produced in this oxide layer by etching, with application of a photo-lithographic technique; these recesses define the cavities for the sensors. Then a second silicon wafer is connected to the first wafer by bonding so that the cavities are created instead of the recesses. Then the first wafer is thinned from the rear side such that a surface of the silicon or SOI layer is exposed. The second wafer assumes the function of the substrate wafer. The part of the silicon layer above the cavity becomes the membrane of the sensor. The exposed surface of the silicon layer is processed further in the subsequent semiconductor production for integration of the transducers or other microelectronic circuit elements.
The German Patent DE 195 43 893 C1 discloses a method of aligning structures to be produced in a substrate, wherein calibration markers are used for calibration of the CMOS planes elative to the cavities in the production process outlined in the foregoing. In this method the calibration markers are etched as trenches into the surface of the first wafer and subsequently filled with a suitable material. The calibration markers and lines required by the stepper are copied. The trenches extend into the first wafer down to a depth that corresponds at least to the remaining thickness of the wafer thinned in a subsequent step so that they penetrate through the thinned silicon layer completely. The markers are therefore clearly visible on the new surface after re-thinning of the wafer. The demands to adjustability are hence satisfied.
One disadvantage of this trench process for the creation of the calibration markers is the necessity of additional process steps. These process steps are required, on the one hand, in order to achieve the deeper depth of the trenches, compared against the cavity structures. On the other hand, the trenches must be additionally filled with a suitable material.
Another disadvantage of this method consists in the requirement of a specific trench-etching process in order to be able to create the trenches in the silicon wafer with a sufficient steepness of the flanks. Moreover, a complex masking layer is required which must resist the intensive plasma etching operation and which is then removed.
A particular disadvantage resides in the aspect that the complete etching of the SOI layer through the layer with subsequent
Bollmann Dieter
Neumeier Karl
Breiner & Breiner L.L.C.
Dang Trung
Fraunhofer Gesellschaft zur Förderung der angewandten Forschung
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