Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2005-06-21
2005-06-21
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S237000, C438S258000, C438S305000, C438S514000, C438S696000, C438S704000, C438S745000
Reexamination Certificate
active
06908839
ABSTRACT:
The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N+source/drain implant and P-channel regions are then opened for P+source/drain implant. Prior to the N+source/drain implant, the wafer receives a patterned first spacer etch. During this first spacer etch, the photosensor region is covered with resist. Prior to the P+source/drain implant, a masked second spacer etch is performed. Again the photosensor region is protected with photoresist. In such a manner, spacers are formed on the gates of both the N-channel and P-channel transistors but in the photodiode region the spacer insulator remains.
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Dickstein , Shapiro, Morin & Oshinsky, LLP
Fourson George
Garcia Joannie Adelle
Micro)n Technology, Inc.
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