Fishing – trapping – and vermin destroying
Patent
1989-09-29
1991-05-07
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 26, 437 62, 437 83, 437132, 437974, H01L 2120
Patent
active
050136810
ABSTRACT:
A process for fabricating thin film silicon wafers using a novel etch stop composed of a silicon-germanium alloy includes properly doping a prime silicon wafer for the desired application, growing a strained Si.sub.1-x Fe.sub.x alloy layer onto seed wafer to serve as an etch stop, growing a silicon layer on the strained alloy layer with a desired thickness to form the active device region, oxidizing the prime wafer and a test wafer, bonding the oxide surfaces of the test and prime wafers, machining the backside of the prime wafer and selectively etching the same to remove the silicon, removing the strained alloy layer by a non-selective etch, thereby leaving the device region silicon layer. In an alternate embodiment, the process includes implanting germanium, tin or lead ions to form the strained etch stop layer.
REFERENCES:
patent: 3721588 (1973-03-01), Hays
patent: 3959045 (1976-05-01), Antypas
patent: 3976511 (1976-08-01), Johnson
patent: 3997381 (1976-12-01), Wanlass
patent: 4116751 (1978-09-01), Zaromb
patent: 4142925 (1979-03-01), King et al.
patent: 4226649 (1980-10-01), Davey et al.
patent: 4230505 (1980-10-01), Wu et al.
patent: 4255208 (1981-03-01), Deutscher et al.
patent: 4292730 (1981-10-01), Ports
patent: 4325073 (1982-04-01), Hughes et al.
patent: 4599792 (1986-07-01), Cade et al.
patent: 4601779 (1986-07-01), Abernathey et al.
patent: 4649627 (1987-03-01), Abernathey et al.
patent: 4851078 (1989-07-01), Short et al.
patent: 4875086 (1989-10-01), Malhi et al.
patent: 4891329 (1990-01-01), Reisman et al.
patent: 4959328 (1990-09-01), Behr et al.
Kimura et al., "Single Crystal Si Film on an Insulating Substrate," Appl. ys. Lett. , 43(3), 1 Aug. 1983, pp. 263-265.
Maszera et al., "Bonding of Silicon Wafers for Silicon-on-Insulator," J. Appl. Phys., vol. 64, No. 10, Pt. 1, 15 Nov. 1988, pp. 4943-4950.
Godbey David J.
Hughes Harold L.
Kub Francis J.
Bunch William D.
Chaudhuri Olik
McDonnell Thomas E.
Root Lawrence A.
Rutkowski Peter T.
LandOfFree
Method of producing a thin silicon-on-insulator layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of producing a thin silicon-on-insulator layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of producing a thin silicon-on-insulator layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-939414