Method of producing a SI-GE base heterojunction bipolar device

Details Method of producing a SI-GE base heterojunction bipolar device Method of producing a SI-GE base heterojunction bipolar device

2000-01-27

2002-02-12

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

C438S309000, C438S343000

Reexamination Certificate

active

06346453

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a method of producing a heterojunction bipolar semiconductor device, and in a particular embodiment, a bipolar transistor and also to a method of producing a semiconductor device including a bipolar transistor having a SiGe base supported by an oppositely doped substrate.
BACKGROUND OF THE INVENTION
To improve the operating speed of a bipolar transistor, it is important that the base layer be thin enough to minimize the time it takes electronic charges to move from the emitter to the collector, thereby minimizing the response time of the transistor, and have a high concentration of dopant in order to minimize base resistance. Typically, ion implantation technique is widely used to form a base layer. However, this technique has a problem of ion channeling, which limits the minimum thickness of the base layer to about 40 nm. Another disadvantage of ion implantation is that the Si/SiGe film is often damaged by the ions, and high temperature annealing is required which alters the concentration profile within the various layers of semiconductor material making up the transistor.
One known technique to avoid the above problem is to form a base layer using an epitaxial technique which precisely defines the base region and inherently has no problem of channelling because the dopants are placed in the semiconductor layer during growth. With this technique, it is possible to form a base layer having a thickness smaller than 30 nm and having an arbitrary impurity concentration or profile by incorporating an impurity directly into the base layer during the epitaxial growth process. Using this technique, a high-speed bipolar transistor having a maximum cut-off frequency f
T
as high as 50 GHz has been realized.
Although the bipolar transistor fabricated with the above technique has such a high maximum cut-off frequency f
T
as a result of the thin base, the engineering trade-off is high base resistance (R
b
) which may limit the maximum frequency of oscillation f
max
to 30-40 GHz.
To further increase the impurity concentration of the base layer to reduce the base resistance (R
b
), it is required to increase not only the impurity concentration of the base layer but also that of the emitter layer so that a sufficiently high current gain (hFE) can be obtained.
However, the further increase in the impurity concentration of the emitter can cause a reduction in bandgap which in turn results in a reduction in the injection efficiency, a reduction in the emitter-base breakdown voltage, and an increase in the emitter-base junction charging time constant &tgr;
EB
. Since the requirements among these parameters conflict with each other, there is a limitation in the improvement in the operating speed.
Notwithstanding, this conflict can be avoided by employing a heterojunction between the emitter and base in which the bandgap of the emitter is different from that of the base. For example, silicon germanium (SiGe) having a narrower bandgap than silicon is used as a base material so as to form a practical heterojunction. In the heterojunction structure, the emitter can inject charge carriers with greater efficiency into the base than the emitter of the homogeneous junction structure. This makes it possible to achieve a sufficiently high current gain without increasing either the base resistance (R
b
) or the emitter-base junction charging time constant &tgr;
EB
, and thus it is possible to realize a high-speed bipolar transistor having a maximum frequency of oscillation f
max
as high as about 100 GHz.
To fabricate a heterojunction bipolar transistor, it is important to control the distributions of p-type impurity and germanium (Ge) across the base layer so that the Ge profile is formed at a precise location with respect to the p-n junction. As was stated earlier, transistor performance is greatly affected by the incorporation of Ge and the concentration profiles of the dopants. Moreover, the interaction of bandgap profile with the dopant profile is also an important factor in the overall design of the transistor and the performance. If the location of the Ge profile—that is, the concentration of Ge versus position with respect to the dopant position is not controlled precisely from wafer to wafer, or from manufacturing lot to manufacturing lot, or even across the wafer, then transistor performance will vary accordingly. In one area of the wafer, for example, transistors with excellent high-frequency response may be realized while at a different location, poor high-frequency response might be seen. Correspondingly, these differences in transistor performance may result in poor circuit yield, and increased circuit testing costs.
With reference to
FIGS. 1A-1C
, a conventional method of producing a junction bipolar transistor is described below.
As shown in
FIG. 1A
, an n
+
buried collector layer
112
is formed on the surface of a silicon substrate
111
by means of solid-state diffusion or ion-implantation. An epitaxial layer
113
with an impurity concentration of 5×10
16
atoms/cm
3
is then epitaxially grown thereon by means of an epitaxial growth technique. The epitaxial layer
113
is locally oxidized (for example by the LOCOS (local oxidation of silicon) method so as to form a device isolation oxide film
14
. The surfaces of the epitaxial layer
113
and the device isolation oxide film
114
can be planarized. In addition, an ion implantation process is then performed either before oxidation or after so that a p
+
device isolation diffusion layer
115
is formed under the device isolation oxide film
114
. Another ion implantation process is performed to form an n
+
collector contact diffusion layer
116
connected to the n
+
buried collector layer
112
.
Then as shown in
FIG. 1B
, a 30 nm thick silicon germanium (Si
0.8
Ge
0.2
) film containing boron (B) acting as a p-type impurity with a concentration of about 3×10
19
atoms/cm
3
is formed over the entire surface area of the epitaxial layer
113
.
A 50 to 80 nm thick silicon film containing an n-type impurity with a concentration of about 3×10
18
atoms/cm
3
is then formed thereon.
Ion implantation and activation annealing are then performed so as to dope the surface region of the emitter layer
118
with an n-type impurity to a high concentration (for example in the range from 1×10
20
atoms/cm
3
to the solid solubility level) thereby forming an emitter contact layer
119
. The activation annealing should be performed in the range from about 850° C. to 900° C. A base and an emitter on the base are then formed by means of a patterning technique.
Subsequently, as shown in
FIG. 1C
, an interlayer insulating film
121
is formed and then contact holes
122
,
123
, and
124
are formed in the interlayer insulating film
121
. Electrodes
125
,
126
, and
127
are then formed such that these electrodes are in contact with the base layer
117
, the emitter contact layer
119
, and the collector contact diffusion layer
116
, respectively, through the contact holes
122
,
123
, and
124
.
In another (second) conventional technique, the base layer, the emitter layer, and the emitter contact layer are formed by means of a low-temperature epitaxial growth process.
In a still another (third) conventional technique, after epitaxially forming the base layer and the emitter layer, an n-type impurity region is formed by means of an ion implantation process.
In the first conventional technique, however, if the base layer is subjected to a heat treatment at a temperature higher than approximately 800° C., diffusion of boron (B) and germanium (Ge) in the base layer occurs. If such a diffusion occurs, the base width will be expanded and discrepancy in position between the bandgap profile and the p-n junction will occur. Furthermore, since the base layer of silicon germanium (SiGe) has a thickness greater than the critical film thickness determined by the thermal equilibrium theory, the high-temperature heat treatment will introduce disloca

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