Method of producing a semiconductor surface covered with...

Details Method of producing a semiconductor surface covered with... Method of producing a semiconductor surface covered with...

2000-09-27

2003-05-20

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C134S001300

Reexamination Certificate

active

06566271

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the semiconductor technology field. More specifically, the present invention relates to a method of producing a semiconductor surface covered with fluorine, and in particular, to a method for producing a semiconductor surface which is covered with fluorine and on which so-called gate oxide or tunnel oxides can subsequently be produced.
In order to maintain or increase competitiveness in the international marketplace, it is necessary to continuously reduce the cost which has to be expended in order to implement a specific electronic function and thus to continuously increase the productivity. This increase in the productivity has been and is primarily achieved by increased integration of the electronic functions. The increase in the integration of the electronic functions in turn is primarily achieved by means of a progressive reduction in the size of the structure of the individual components. At the same time, it is to be considered as fortunate that the additional requirements for faster circuits and a lower power loss can likewise be met by the use of smaller and smaller structures.
Accordingly, the aim of many developments is to provide new processes which permit the production of smaller and yet smaller structures in a cost-effective way. At the same time, the production processes must satisfy several other conditions. For example, on the one hand it is necessary to optimize the parameters of the components in accordance with the desired electronic function. On the other hand, it is necessary to ensure adequate stability of these parameters over the lifetime of the component. Unfortunately, several degradation mechanisms exist which have a detrimental effect on the electrical parameters of the individual components.
The degradation mechanism which has been most investigated is the so-called HE degradation (HE=hot electron). During the operation of an MOS transistor, a field-strength peak occurs at the drain-side channel edge and can accelerate the channel electrons to a value that is close to their limiting speed. Some of these so-called hot electrons are able to overcome the potential barrier at the gate-oxide interface and jump into the gate oxide. There, among other things, these electrons can break down Si—H bonds and thus produce interface states. In an n-channel MOS transistor, the hot-electron effects primarily manifest themselves in degradation of the drain current. In a p-channel MOS transistor, the hot electron effects primarily manifest themselves in a shortening of the effective channel length.
In addition to the degradation of the transistor parameters by hot electrons, an important part is played by the degradation of the transistor parameters as a result of the application, lasting over a relatively long time period, of a gate voltage at elevated temperatures (Bias Temperature Stress, BTS), in particular for analog or mixed analog/digital circuit functions.
In analog or mixed analog/digital circuit functions, some of the MOS transistors are often operated at an operating point which reacts very sensitively to changes in the turn-on voltage of the transistor. This operating point is characterized by a gate voltage which lies only slightly above the turn-on voltage of the MOS transistor. Consequently, even small fluctuations in the turn-on voltage of the MOS transistor lead to relatively large fluctuations in the current which flows through the MOS transistor at the operating point. Since typical applications in analog circuit functions need a current which is defined as well as possible through the respective MOS transistor, fluctuations of this type in the turn-on voltage of the MOS transistor generally cannot be accepted. Unfortunately, degradation resulting from bias temperature stress (BTS) leads precisely to a change in the turn-on voltage, with the aforementioned negative effects on the analog circuit functions.
The long-term stability of the electrical parameters also plays an important role in erasable programmable read-only memories (EPROM, EEPROM). In those read-only memories, the programable elements are MOS transistors which in each case have an additional, electrically insulated polysilicon gate (floating gate). For the purpose of programming, this polysilicon gate is charged up by a tunnel current flowing through a thin oxide (tunnel dielectric). However, the tunneling charge carriers produce further interface states, which result in an increase in the conductivity of the oxide and/or a reduction in the breakdown voltage. This can in turn lead to a memory cell failing during operation.
In order to avoid these degradation mechanisms and to increase the long-term stability, several measures have been proposed. As an effective counter-measure to HE degradation, use is generally made nowadays of a so-called LDD doping (LDD=lightly doped drain) of the source/drain regions of a MOS transistor. This LDD doping requires additional process steps, however, which has a negative effect on the manufacturing costs.
In order to solve the problem of the drift in analog circuits which is caused by the bias temperature stress, hitherto measures purely involving circuitry have generally been taken. The intention of these circuit-based measures is to prevent a voltage being applied to the gate of an MOS transistor over a relatively long time period. However, the aforementioned circuit-based measures complicate the design of the circuit and in addition cost additional chip area, which therefore cannot be used for other electronic circuit functions.
In addition, it has been proposed to introduce small amounts of fluorine or chlorine into the oxide layers in order to increase their long-term stability. See, for example, Wright and Saraswat, “The Effect of Fluorine in Silicon Dioxide Gate Dielectrics”, IEEE Transactions on Electron Devices, Vol. 36, No. 5, May 1989; or Chen et al., “Performance and Reliability Enhancement for CVD Tungsten Polycided CMOS Transistors due to Fluorine Incorporation in the Gate Oxide”, IEEE Electron Device Letters, Vol. 15, No. 9, September 1994).
In the processes used hitherto for introducing fluorine into the oxide layers, the fluorine defuses through the oxide layer to the semiconductor interface. However, the diffusion of fluorine damages the structure of the oxide layer in such a way that the further diffusion of dopants through the oxide layer is no longer adequately prevented. The consequence of this is that the reduction achieved in this way, for example in the HE degradation, is generally not sufficient to justify the additional cost which is entailed by the introduction of fluorine or chlorine into the gate oxide. In addition, during the diffusion of the fluorine through the oxide layer, the amount of fluorine which is ultimately available at the semiconductor interface can be defined only very inaccurately. Accordingly, this method is generally not used in mass production.
U.S. Pat. No. 5,181,985 describes semiconductor cleaning processes. There, the surface of a semiconductor substrate is repeatedly fed with water vapor and gaseous hydrogen fluoride, and the semiconductor surface is subsequently rinsed with water.
U.S. Pat. No. 5,098,866 describes a process for oxide-back etching, in which, inter alia, hydrogen fluoride is supplied for the purpose of etching.
U.S. Pat. No. 5,022,961 describes a process for cleaning semiconductor surfaces in which hydrogen fluoride and alcohol are brought into contact with a substrate surface. In that process, a thin alcohol layer remains on the substrate surface. It is used to protect inadvertent oxidation and it can be removed if required.
SUMMARY OF THE INVENTION
The object of the invention is to provide a method of producing a semiconductor surface with fluorine which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which provides for a fluorine-laden surface on which oxide layers of high quality can subsequently be produced, so that the probl

Affiliated with

Also associated with

Rating

Method of producing a semiconductor surface covered with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of producing a semiconductor surface covered with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of producing a semiconductor surface covered with... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3001080