Method of producing a semiconductor device using feature...

Details Method of producing a semiconductor device using feature... Method of producing a semiconductor device using feature...

2001-03-21

2003-04-29

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S636000, C438S671000, C438S720000, C438S725000

Reexamination Certificate

active

06555472

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of producing a semiconductor device using feature trimming to obtain a feature definition smaller than the lithographic resolution limit. The present invention in particular relates to a method of producing a semiconductor device using a lithographic method for producing a resist feature on a surface of the semiconductor and of etching the resist feature in a lateral direction using a reactivity-inhibited etchant.
2. Description of the Related Art
The manufacturing process of integrated circuits involves the fabrication of numerous insulated gate field-effect transistors, such as metal-oxide semiconductor field-effect transistors (MOSFETs). In order to increase integration density and improve device performance, for instance, with respect to signal processing time and power consumption, feature sizes of the transistor structures are steadily decreasing. Most importantly, the gate length of the fabricated transistors needs to be reduced to comply with these requirements.
In a field-effect transistor, such as a MOSFET, the gate electrode is used to control an underlying channel formed in the semiconductor substrate between a source region and a drain region. The channel, source region, and drain region are formed in, on, and/or over a semiconductor substrate that is doped inversely to the drain and source regions. The gate electrode is separated from the channel, the source region, and the drain region by a thin insulating layer, generally an oxide layer.
The formation of the gate electrode is a critical step in the manufacturing process of the field-effect transistor. The gate length dimension, i.e., the lateral extension of the gate electrode between the source region and the drain region of the field-effect transistor in the direction of the current flow path, is commonly known as a critical dimension of the gate electrode. This critical dimension is desirably reduced to sizes approaching or even exceeding the resolution limit of the lithographic systems used for patterning the device features.
Conventionally, device features are defined and delineated by lithographic techniques, in particular photolithography, preferably using a high numerical aperture lens and a deep ultraviolet (DUV) light source. Current DUV lithography reaches its resolution limit at a feature size of approximately 0.2 &mgr;m (200 nm).
Currently, metal-oxide semiconductor (MOS) transistor with gate lengths in the sub-100 nm range can not easily be obtained with the generally known DUV lithography technology. Other production methods used to obtain such gates in the sub-100 nm range, like electron beam patterning, have reduced throughput and yield, and are, therefore, a significant contributor to the cost of manufacturing in the semiconductor industry. Such an MOS transistor gate in the sub-100 nm range is, however, necessary to obtain small semiconductor devices, which are required, i.e., for increasing clock frequencies in processors used in computers, and for keeping the gate current as low as possible to achieve a nearly ideal voltage amplification.
To meet the above requirements, there is a demand for a technique to delineate feature sizes beyond the resolution limit of DUV lithography. To comply with the general requirements of mass production of semiconductor devices, any new technology must conserve the current standards of efficiency, reliability and cost of already existing methods or provide improvements in this respect.
In view of the above-mentioned problems, a need exists for a method for patterning gate electrodes of field-effect transistors in integrated circuits to a size smaller than the resolution limit of currently available standard DUV photolithography tools, currently about 200 nm.
The present invention is directed to a method of making a semiconductor device that solves, or at least reduces, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
This invention provides a method of producing semiconductor devices having feature sizes smaller than the resolution limit of the lithography used for feature definition.
According to one aspect of the invention there is provided a method of producing a semiconductor device comprising: providing a semiconductor substrate having a surface, forming a layer of gate electrode material above the surface of said the semiconductor substrate, and forming a resist feature above the layer of the gate electrode material. The method also comprises the resist feature having a lateral dimension, reducing the lateral dimension of the resist feature, and patterning at least the layer of gate electrode material using the resist feature with the reduced lateral dimension.
According to another aspect of the invention there is provided a method of producing a semiconductor device comprising: providing a semiconductor substrate having an anti-reflective coating layer and a surface over the anti-reflective coating layer, forming a layer of gate electrode material above the surface, and forming a resist feature above the layer of the gate electrode material. The method also comprises the resist feature having a lateral dimension, reducing the lateral dimension of the resist feature by etching the resist feature during a plasma etch-process comprising hydrogen iodine and oxygen plasmas, having an etch-rate in the lateral direction, and patterning at least the layer of gate electrode material using the resist feature with the reduced lateral dimension.
According to the present invention, a more precise shrinkage of the gate length of an MOS transistor can be achieved, if the gate-forming resist feature is shrunk rather than the final gate electrode. The invention described herein enables a significant reduction of MOS transistor gate dimensions and, therefore, of the whole MOS transistor, and, consequently, a significant reduction in power consumption of the device and an increase in processing speed can be achieved.


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Toshiharu (JP-05275393) (Translation).

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