Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2003-02-19
2004-08-10
Lee, Hsien Ming (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S180000, C438S184000, C438S195000
Reexamination Certificate
active
06773970
ABSTRACT:
This application claims priority to Japanese Patent Application Number JP2002-046393 filed Feb 22, 2002, which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of producing a semiconductor device, more particularly relates to a method of producing a semiconductor device having a gate electrode doped with an impurity at a high concentration.
2. Description of the Related Art
Due to the increased miniaturization of semiconductor chips, the degree of integration has been doubling every three years according to the scaling rule. Along with this, faster speeds and lower consumption of energy have been achieved. The transistors of semiconductor chips are being miniaturized by reduction of the size of the electrodes and reduction of the thickness of gate insulating films.
Transistors can be also miniaturized by controlling precisely the impurity profile of a channel formation region of the transistor or its vicinity to form a shallow junction. Miniaturization of transistors enables improvement of the drive capability of transistors and decrease of the parasitic capacitance etc.
Up to now, polysilicon doped with an impurity at a high concentration has been often used as an gate electrode.
FIG. 1
is a cross-sectional view of a gate electrode made of doped polysilicon. As shown in
FIG. 1
, a silicon wafer
21
is separated into element formation regions by element isolation regions
22
. A gate electrode
24
is formed on an element formation region of the silicon wafer
21
via a gate insulating film
23
. For example, a silicon oxide film is formed above the gate electrode
24
and the silicon substrate
21
as an interlayer insulating film
25
.
FIG. 2
is an enlarged view of a part of the gate electrode
24
of FIG.
1
. Various types of heat treatment are conducted during the process for formation of a semiconductor chip. For example, when using p
+
-type polysilicon doped with boron (B) as the gate electrode
24
, depending on the conditions of heat treatment conducted after doping the boron into the gate electrode
24
, the boron in the gate electrode
24
will precipitate on the silicon oxide film of the interlayer insulating film
25
etc. (boron precipitation part
26
) and the boron will diffuse in the silicon oxide film at a relatively high speed (boron diffusion path
27
).
When an impurity diffuses from the gate electrode
24
to the interlayer insulating film
25
along with heat treatment, the part of the gate electrode
24
near the interface with the interlayer insulating film
25
becomes depleted. Due to this, the drive capability of the transistor is lowered and/or the work function (threshold of transistor) fluctuates.
Along with miniaturization of the gate electrodes, the problem described above of the outward diffusion of the impurity in the doped polysilicon gate electrode tends to become more prominent. When miniaturizing a gate electrode, the aspect ratio of the gate electrode increases. Due to this, the amount of diffusion of the impurity in the gate electrode from the side surfaces of the gate electrode to the insulating film increases. As a result, it becomes more difficult to prevent deterioration and/or fluctuation of the device performance.
The diffusion of the impurity from the side surfaces of the gate electrode is observed not only in the case of using a single layer of p
+
-type polysilicon as the gate electrode, but also in a gate electrode of polycide structure wherein a refractory (heat resistant) metal silicide layer is formed on p
+
-type polysilicon or in a gate electrode of a polymetal structure wherein a refractory metal or other metal layer is formed on p
+
-type polysilicon via a barrier metal.
Although the silicon oxide films are represented by the same composition (SiO
2
), the diffusion coefficient of boron is generally larger in the interlayer insulating film than in the gate oxide film. Therefore, the concentration of boron in the p
+
-type polysilicon gate electrode is apt to decrease particularly at the vicinity of the interface with the silicon oxide film of the interlayer insulating film.
In this case, the polysilicon at the vicinity of the surface or side surfaces of the gate electrode becomes depleted and the work function of p
+
-polysilicon fluctuates locally. Due to this, in a transistor using p
+
-type polysilicon as a gate electrode, the fluctuation of various characteristics, commencing with the threshold Vth, increases.
On the other hand, in the case of n
+
-type polysilicon gate electrodes doped with phosphorous (P), the phosphorous atoms in the gate electrode pile up at the interface with the silicon oxide film. Therefore, in this case too, the concentration of the impurity in the polysilicon decreases at the vicinity of the interface of the polysilicon and the silicon oxide film.
Of the above, the amount of the impurity leaking from the side surfaces of the gate electrode particularly changes depending on the gate length Lg and gate width Wg of each pattern of gate electrodes. Therefore, it cannot be controlled equally over the entire LSI. The amount of an impurity leaking from a gate electrode relatively increases along with miniaturization of the gate electrode. Particularly, when the gate length is 0.1 &mgr;m or less, depletion of the gate electrode due to escape of an impurity becomes predominant. Therefore, the drive capability of current of a transistor does not improve even if the gate electrode is miniaturized (see Murakami et al., Technical Report of IEICE Information and Communication Engineers SDM 2001-48, pp. 25.)
Japanese Unexamined Patent Publication (Kokai) No. 10-303410 proposes, as a method of prevention of outward diffusion of an impurity in a gate electrode, a method of covering the entire gate electrode with a capping layer.
FIG. 3
shows the structure of a gate electrode disclosed in the publication.
The structure of
FIG. 3
is one wherein a silicon nitride film
28
(Si
3
N
4
film) and side wall spacer
29
made of a silicon nitride film are provided as a capping layer. The silicon nitride film
28
and side wall spacer
29
are formed by low-pressure chemical vapor deposition (LP-CVD) or another method. According to this method, diffusion of an impurity from the top surface and side surfaces of a gate electrode can be prevented effectively.
However, according to the structure and method disclosed in the above Japanese Unexamined Patent Publication (Kokai) No. 10-303410, since the entire gate electrode is capped with a relatively thick silicon nitride film, the following problems arise. These make it difficult to apply this technique for all miniaturized devices of the next generation.
When capping a gate electrode with a relatively thick silicon nitride film, the stress of the silicon nitride film increases relatively along with miniaturization of the gate electrode. Due to the stress, depending on the circumstances, the gate electrode may peel off, the energy level of the interface with the gate insulating film may increase, or other phenomena may arise.
Also, to cap a gate electrode with a silicon nitride film, it is necessary to form a silicon nitride film over the entire surface, then remove part of the silicon nitride film by dry etching leaving only the silicon nitride film covering the gate electrode. This etching is performed anisotropically using the base silicon substrate as a stopper.
Since the etch selectivity of silicon nitride with respect to silicon is difficult to increase in principle, it is impossible to completely prevent etching of the base silicon while etching the silicon nitride film.
In recent years, as a transistor able to drastically decrease the junction capacitance, a transistor of an SOI structure has been produced. When forming the gate electrode described in Japanese Unexamined Patent Publication (Kokai) No. 10-303410 on an SOI having a thin silicon active layer, during a dry etching step of the silicon nitride film to process the capping
Depke Robert J.
Holland & Knight LLP
Lee Hsien Ming
SonyCorporation
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