Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-20
2001-10-30
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S654000, C438S685000, C438S612000, C438S138000
Reexamination Certificate
active
06309965
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a silicon semiconductor body, which can be soldered to a metal substrate plate via a succession of metal layers, and which before the soldering, in order from the silicon to the substrate plate, has an aluminum layer and a diffusion barrier layer.
Such semiconductor bodies are incorporated into semiconductor elements, especially power semiconductor elements, which are on the market in great numbers. The sequence of metal layers as a rule includes an aluminum layer, which is seated on a silicon semiconductor body. The aluminum layer adheres well to the silicon and form a perfect ohmic contact, especially with p-doped silicon. In the prior art, a diffusion barrier layer, which is usually of titanium or chromium, is seated on the aluminum layer and acts as an adhesion promoter and back-side barrier between a further metal layer, as a rule a nickel layer, seated on the diffusion barrier layer, and the aluminum layer.
Because the coefficients of thermal expansion are different for the individual metal layers on the one hand and for the silicon semiconductor body on the other, severe mechanical stresses are engendered. Especially in thin semiconductor bodies, that is, semiconductor bodies that have a thickness of 250 &mgr;m or less, severe warping of the wafer occurs, that is, warping greater than 1000 &mgr;m.
This makes handling of the wafers more difficult; increased cassette positioning mistakes occur, and there is an increased danger of breakage. Until now, the attempt was made to solve the problem by minimizing the nickel layer thickness as much as possible, so that the soldering still had adequate adhesion strength. Despite reduced nickel layer thicknesses, that is, layer thicknesses of approximately 1 &mgr;m, nevertheless in production wafer warping of 700 to 2000 &mgr;m still occurs and leads to the above problems.
Particularly with a view to the desire for ever-thinner semiconductor bodies, that is, semiconductor bodies that have a thickness of approximately 100 &mgr;m, there is a need for a metallizing process that helps solve the above problems. Such semiconductor bodies are needed particularly in power field effect transistors and IGBTs of the vertical type.
Published, Non-prosecuted German Patent Application DE 38 23 347 A1 describes a semiconductor element having a high current carrying capacity and a contact layer construction of the semiconductor body. The metallizing includes a first layer of aluminum, a second layer of chromium or titanium as an adhesion layer and as a diffusion barrier for the aluminum, a solderable third layer of nickel, and a concluding protective layer of gold or palladium, or of a solderable layer each with a partial layer of nickel and copper. The copper at the same time is the outermost layer or can also be covered with gold or palladium.
In IEEE Transactions on Electron Devices, 1986, Vol. ED-33, No. 3, pages 402-408, a silicon power transistor with a stepped electrode structure and a titanium nitride diffusion barrier is described. The titanium nitride diffusion barrier layer is applied, in the form of a succession of titanium, titanium nitride, and titanium, between a gold electrode terminal and a silicon substrate. As a result, high reliability and a long service life of the bond are attained, and a gold-silicon reaction is prevented.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor body with a metallizing on the back side that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which wafer warping is markedly reduced without losses of adhesion strength to the substrate materials.
With the foregoing and other objects in view there is provided, in accordance with the invention, a layered semiconductor configuration to be soldered to a metal substrate plate, including: a silicon semiconductor body; an aluminum layer disposed on the silicon semiconductor body; a titanium layer disposed on the aluminum layer; and a titanium nitride layer disposed in the titanium layer and acting as a diffusion barrier layer.
The object is attained in that a titanium layer into which a titanium nitride layer is incorporated is provided as the diffusion barrier layer.
Surprisingly, it has been found that by incorporating a titanium nitride layer into the titanium layer acting as a diffusion barrier layer, a majority of the incident wafer warping can be compensated for.
Typically, onto the thus-processed diffusion barrier layer, a nickel layer is then applied, onto which, either with the deposition of an adhesion promoter layer or without an adhesion promoter layer, an oxidation protection layer, preferably a silver layer, is applied.
In an alternative version of the present invention, a solder material layer, which preferably includes tin or lead or gallium, is deposited onto the titanium layer. By this procedure, the semiconductor body can be soldered directly to the substrate plate by heating to temperatures above approximately 250°, without having to solder a separate solder material layer to an nickel layer. It is then unnecessary to add other soldering agents and fluxes.
The solder layers thus created are virtually stress-free, so that only marginal substrate warping occurs.
The semiconductor body of silicon in accordance with the present invention is typically produced by the following method. The method of the invention includes the following steps:
a) an aluminum layer is deposited onto the semiconductor body;
b) a first titanium layer is deposited onto the aluminum layer;
c) a titanium nitride layer is deposited onto the titanium layer;
d) a second titanium layer is deposited on to the titanium nitride layer.
Especially good back-side metallizing is attained by first applying a thin aluminum layer to the semiconductor body and then tempering the thus-processed semiconductor body, preferably at approximately 350° C. Once the tempering has been done, a further aluminum layer is deposited onto the first aluminum layer.
Because of the two parts of the aluminum coating process and the in-situ tempering of the aluminum-coated semiconductor body, the effect of the incorporated titanium nitride layer in the titanium layer is especially well stabilized. It has in fact been found that by shifting the tempering step from the end of the metallizing process to the aluminum coating process, the favorable properties of the titanium nitride layer are largely preserved.
If the tempering step were done at the end of the metallizing, then the favorable property of the titanium nitride layer would be negatively affected; that is, in the worst case, approximately 50% of the stress-compensating properties of the titanium nitride layer would be lost.
Shifting the tempering step from the end of metallizing to the aluminum coating process causes no impairment of the overall metallizing process, since the tempering step serves merely to establish an especially good contact between aluminum and silicon.
Typically, all the metal layers in the method of the invention are vapor-deposited.
After method step d) has been performed, it is possible, depending on which procedure is desired, to deposit a nickel layer onto the titanium layer, with an ensuing deposition of an oxidation protection layer. Between the deposition of the oxidation protection layer and the nickel layer, the deposition of an adhesion promoter layer can optionally be done, and this layer again can include titanium.
In an alternative embodiment, however, the application of a solder material layer of tin, lead or gallium is done directly after method step d).
Typically, all the metal layers are vapor-deposited.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor body with a metallizing on the back side, it is nevertheless not intended to be limited to the details shown, since various modifications and struc
Laska Thomas
Mascher Herbert
Matschitsch Martin
Matzler Andreas
Moik Gernot
Bowers Charles
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Smoot Stephen W.
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