Method of processing semiconductor wafer

Details Method of processing semiconductor wafer Method of processing semiconductor wafer

2011-03-08

2011-03-08

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Plural fluid growth steps with intervening diverse operation

C438S498000, C438S504000, C257SE21092

Reexamination Certificate

active

07902053

ABSTRACT:
Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.

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patent: 2005/0006699 (2005-01-01), Sato et al.
patent: 2005/0048701 (2005-03-01), Minato et al.
patent: 2009/0085149 (2009-04-01), Ishida et al.
patent: WO-02/067333 (2002-08-01), None
Ishida, H. et al., U.S. Office Action mailed Oct. 22, 2009, directed to U.S. Appl. No. 12/236,348; 9 pages.
Ishida, H. et al., U.S. Office Action mailed on Apr. 15, 2010, directed to related U.S. Appl. No. 12/236,348; 11 pages.

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