Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-09-03
2001-07-24
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S303000, C438S664000, C438S672000, C438S643000
Reexamination Certificate
active
06265295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of preventing tilting of metal contact structures for quarter micron and deep sub-micron polysilicon gate devices.
2. Description of the Prior Art
Recent advances in the manufacturing of semiconductor devices have led to dramatic reductions of device feature sizes while simultaneously increasing device density and device performance, all the while keeping device production costs within severe competitive constraints. One of the devices that is used extensively for Ultra Large Scale Integration (ULSI) is the Field Effect Transistor (FET). The FET is typically fabricated on the surface of a semiconductor substrate by first creating a thin layer of oxide over the surface of the substrate. This layer of oxide serves as a stress release layer. Polysilicon gate electrodes are next patterned over the layer of oxide forming the gate electrode structure of the FET device. Insulating gate spacers are patterned over the polysilicon gate electrodes. Self-aligned source and drain regions are implanted adjacent to the gate electrodes thereby using the gate electrodes as implant or diffusion masks. Device performance can be significantly improved by reducing the sheet resistance of the surface of the polysilicon gate electrode and the regions where the metal contacts to the source/drain areas are established. The salicide process is used for this purpose by depositing a metal over the polysilicon gate electrodes and the self-aligned source/drain regions. The deposited metal is sintered thereby forming a silicide layer on the surface of the gate electrode and over the source and drain regions. Care must be taken during this process of selective removal of the unreacted metal to assure that no residual metal remains in place and that all silicide stringers, that potentially can extend over the gate spacers into the top surface of the gate electrode causing electrical shorts between the source/drain regions and the gate electrode, are removed.
The distance between the source and drain regions underneath the gate structure and within the surface of the substrate is the channel length of the gate. Present day devices use device structures where the gate width is in the quarter micron and deep sub-micron region. This severe reduction in device feature sizes is made possible by significant advances in supporting technologies such as the photolithographic process and anisotropic etching techniques. With the reduction of the gate width has come a reduction in channel length where present applications use channel width that are less than the above indicated gate width.
In order to form metal contacts to regions within semiconductor devices, an opening is etched through a dielectric layer so that an upper metal layer can be interconnected with a lower conductive layer. Metal contacts that are established in this manner do not need to be limited to metal contacts to source/drain regions and the gate electrode of a FET but can for instance include strap contacts in logic applications or bit line contacts in a DRAM.
FIG. 1
(to be discussed later) shows an example of Prior Art formation of such a bit line contact in a DRAM.
Typically, a nitride etch stop layer is deposited on the region where the metal contact is to be established, this is followed by depositing a dielectric oxide layer, and then a photoresist is formed on the oxide layer which is patterned to define the desired pattern of openings that are to be etched through the underlying oxide layer. The oxide layer is selectively etched to the underlying nitride etch stop layer, the exposed nitride layer is removed (e.g. by hot H
3
PO
4
) and a liner (e.g. Ti/TiN) and contact metal (e.g. tungsten) are deposited in the openings followed by surface planarization of the device and removal of the photoresist.
It is important to point out that dry etching, such as plasma etching and reactive ion etching, has become the technology of choice in patterning various layers that are formed over a silicon wafer as it is processed to form therein high density integrated circuit devices. This is because it is a process that not only can be highly selective in the materials it etches, but also highly anisotropic. This makes possible etching with nearly vertical sidewalls.
As the downscaling in device feature sizes continues, the creation of these device features experiences a number of problems. With the further decrease in linewidth and decrease in the diameter of the openings that are created in semiconductor devices, the supporting photolithography technology has met these challenges by decreasing the wavelength of the photo exposure that is used to create the patterned layers of photoresist and which are used to define the dimensions of the linewidth and openings that are created in for instance layers of dielectric or etch stop layers. Currently, photo exposure radiation using Near Ultra-Violet (NUV) exposure with a wavelength of 365 nm is applied; this enables the creation of device features down to the 0.35-micron range. The most advanced photo exposure techniques use Deep Ultra Violet (DUV) exposure with a wavelength of 245 nm that enables the creation of device features down to the 0.18 um range. While the photolithography technology will continue to increase its exposure capabilities in support of decreasing device feature sizes, it is also important to provide methods and materials that further assist in the reduction of semiconductor device features. These methods will assist and facilitate design efforts and advances in the field of photolithography that combined will enable future progress in reducing device features and, with that, progress in improved device performance.
FIG. 1
provides an overview of the Prior Art creation of metal contact for a typical DRAM cell. The DRAM structure is formed on the surface of a semiconductor substrate
10
. The formation of the DRAM cell starts with the isolation of the active area of the DRAM by means of the layer
12
of LOCOS that is formed around the active area. A layer of Field Oxide (FOX) is also typically used for this purpose; the isolating layer of oxide is a relatively thick layer of oxide between about 3000 and 6000 Angstrom. For the silicon substrate, typically a P-type single crystal with a crystallographic orientation of (100) is used. A thin (about 100 Angstrom thick) layer of gate oxide (not shown) is grown over the silicon surface to serve as stress release. A layer
14
of polysilicon is blanket deposited over which a layer of insulating material (not shown) is deposited. These two layers are patterned and etched to form gates
14
within the active area of the device and gates
18
on the surface of the LOCOS insulating area of the device. Gates
14
in the active area of the device form the gates of the MOSFET device, gates
18
form the word lines that connect the MOSFET gates to the peripheral circuits that are connected to the DRAM chip. The Lightly Doped (LDD) regions
20
and
22
for the source and drain regions of the N-channel MOSFET are then formed, typically by implant of an N-type dopant such as arsenic or phosphorous. Next the gate spacers
16
are formed over the surface of the patterned polysilicon gates
14
and
18
. These spacers are typically formed by blanket depositing of a layer of low temperature silicon oxide and etching this layer anisotropically to the surface of the substrate. The source
24
and drain
26
regions are formed by implant with an N-type dopant, for instance arsenic. The self-aligned bit-line contact and the self-aligned storage node contacts
29
are formed by conventional methods of lithography and patterning. One (or more) layers
30
of insulation are then deposited over the structure to provide protection from further processing steps. The insulating layer may contain silicon oxide or silicon nitride. Over the insulating layer a further layer of dielectric may be deposited.
The self-alig
Liaw Jhon-Jhy
Lin Yi-Miaw
Yaung Dun-Nian
Ackerman Stephen B.
Anya Igwe U.
Saile George O.
Smith Matthew
Taiwan Semiconductor Manufacturing Company
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